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| author | Richard Osborne <richard@xmos.com> | 2009-11-18 23:20:42 +0000 | 
|---|---|---|
| committer | Richard Osborne <richard@xmos.com> | 2009-11-18 23:20:42 +0000 | 
| commit | 3bd09434a6fcef73d7d3f93f8c64f9c8965c683d (patch) | |
| tree | 2101893a424c75a531cdb519d54dbf68485113b4 | |
| parent | 361a3768796d8f3ead8c8764b52ad5a792cabed8 (diff) | |
| download | bcm5719-llvm-3bd09434a6fcef73d7d3f93f8c64f9c8965c683d.tar.gz bcm5719-llvm-3bd09434a6fcef73d7d3f93f8c64f9c8965c683d.zip  | |
Add XCore support for indirectbr / blockaddress.
llvm-svn: 89273
| -rw-r--r-- | llvm/lib/Target/XCore/AsmPrinter/XCoreAsmPrinter.cpp | 2 | ||||
| -rw-r--r-- | llvm/lib/Target/XCore/XCoreISelLowering.cpp | 15 | ||||
| -rw-r--r-- | llvm/lib/Target/XCore/XCoreISelLowering.h | 1 | ||||
| -rw-r--r-- | llvm/lib/Target/XCore/XCoreInstrInfo.td | 6 | ||||
| -rw-r--r-- | llvm/test/CodeGen/XCore/indirectbr.ll | 45 | 
5 files changed, 68 insertions, 1 deletions
diff --git a/llvm/lib/Target/XCore/AsmPrinter/XCoreAsmPrinter.cpp b/llvm/lib/Target/XCore/AsmPrinter/XCoreAsmPrinter.cpp index d7106a02833..2a561c633b5 100644 --- a/llvm/lib/Target/XCore/AsmPrinter/XCoreAsmPrinter.cpp +++ b/llvm/lib/Target/XCore/AsmPrinter/XCoreAsmPrinter.cpp @@ -333,6 +333,8 @@ void XCoreAsmPrinter::printOperand(const MachineInstr *MI, int opNum) {    case MachineOperand::MO_JumpTableIndex:      O << MAI->getPrivateGlobalPrefix() << "JTI" << getFunctionNumber()        << '_' << MO.getIndex(); +  case MachineOperand::MO_BlockAddress: +    GetBlockAddressSymbol(MO.getBlockAddress())->print(O, MAI);      break;    default:      llvm_unreachable("not implemented"); diff --git a/llvm/lib/Target/XCore/XCoreISelLowering.cpp b/llvm/lib/Target/XCore/XCoreISelLowering.cpp index 16e68fe7b2d..00dcce653ee 100644 --- a/llvm/lib/Target/XCore/XCoreISelLowering.cpp +++ b/llvm/lib/Target/XCore/XCoreISelLowering.cpp @@ -111,7 +111,8 @@ XCoreTargetLowering::XCoreTargetLowering(XCoreTargetMachine &XTM)    setOperationAction(ISD::JumpTable, MVT::i32, Custom);    setOperationAction(ISD::GlobalAddress, MVT::i32,   Custom); -   +  setOperationAction(ISD::BlockAddress, MVT::i32 , Custom); +    // Thread Local Storage    setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom); @@ -158,6 +159,7 @@ LowerOperation(SDValue Op, SelectionDAG &DAG) {    {    case ISD::GlobalAddress:    return LowerGlobalAddress(Op, DAG);    case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG); +  case ISD::BlockAddress:     return LowerBlockAddress(Op, DAG);    case ISD::ConstantPool:     return LowerConstantPool(Op, DAG);    case ISD::JumpTable:        return LowerJumpTable(Op, DAG);    case ISD::LOAD:             return LowerLOAD(Op, DAG); @@ -288,6 +290,17 @@ LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG)  }  SDValue XCoreTargetLowering:: +LowerBlockAddress(SDValue Op, SelectionDAG &DAG) +{ +  DebugLoc DL = Op.getDebugLoc(); + +  BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress(); +  SDValue Result = DAG.getBlockAddress(BA, DL, /*isTarget=*/true); + +  return DAG.getNode(XCoreISD::PCRelativeWrapper, DL, getPointerTy(), Result); +} + +SDValue XCoreTargetLowering::  LowerConstantPool(SDValue Op, SelectionDAG &DAG)  {    ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op); diff --git a/llvm/lib/Target/XCore/XCoreISelLowering.h b/llvm/lib/Target/XCore/XCoreISelLowering.h index 10631afb020..f86be5ea782 100644 --- a/llvm/lib/Target/XCore/XCoreISelLowering.h +++ b/llvm/lib/Target/XCore/XCoreISelLowering.h @@ -120,6 +120,7 @@ namespace llvm {      SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG);      SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG);      SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG); +    SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG);      SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG);      SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG);      SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG); diff --git a/llvm/lib/Target/XCore/XCoreInstrInfo.td b/llvm/lib/Target/XCore/XCoreInstrInfo.td index 4ed4ed4499a..d4ae49e4690 100644 --- a/llvm/lib/Target/XCore/XCoreInstrInfo.td +++ b/llvm/lib/Target/XCore/XCoreInstrInfo.td @@ -679,6 +679,12 @@ def LDAP_lu10 : _FLU10<                    "ldap r11, $addr",                    [(set R11, (pcrelwrapper tglobaladdr:$addr))]>; +let Defs = [R11], isReMaterializable = 1 in +def LDAP_lu10_ba : _FLU10<(outs), +                          (ins i32imm:$addr), +                          "ldap r11, $addr", +                          [(set R11, (pcrelwrapper tblockaddress:$addr))]>; +  let isCall=1,  // All calls clobber the the link register and the non-callee-saved registers:  Defs = [R0, R1, R2, R3, R11, LR] in { diff --git a/llvm/test/CodeGen/XCore/indirectbr.ll b/llvm/test/CodeGen/XCore/indirectbr.ll new file mode 100644 index 00000000000..a8f00cc497f --- /dev/null +++ b/llvm/test/CodeGen/XCore/indirectbr.ll @@ -0,0 +1,45 @@ +; RUN: llc < %s -march=xcore | FileCheck %s + +@nextaddr = global i8* null                       ; <i8**> [#uses=2] +@C.0.2070 = private constant [5 x i8*] [i8* blockaddress(@foo, %L1), i8* blockaddress(@foo, %L2), i8* blockaddress(@foo, %L3), i8* blockaddress(@foo, %L4), i8* blockaddress(@foo, %L5)] ; <[5 x i8*]*> [#uses=1] + +define internal i32 @foo(i32 %i) nounwind { +; CHECK: foo: +entry: +  %0 = load i8** @nextaddr, align 4               ; <i8*> [#uses=2] +  %1 = icmp eq i8* %0, null                       ; <i1> [#uses=1] +  br i1 %1, label %bb3, label %bb2 + +bb2:                                              ; preds = %entry, %bb3 +  %gotovar.4.0 = phi i8* [ %gotovar.4.0.pre, %bb3 ], [ %0, %entry ] ; <i8*> [#uses=1] +; CHECK: bau +  indirectbr i8* %gotovar.4.0, [label %L5, label %L4, label %L3, label %L2, label %L1] + +bb3:                                              ; preds = %entry +  %2 = getelementptr inbounds [5 x i8*]* @C.0.2070, i32 0, i32 %i ; <i8**> [#uses=1] +  %gotovar.4.0.pre = load i8** %2, align 4        ; <i8*> [#uses=1] +  br label %bb2 + +L5:                                               ; preds = %bb2 +  br label %L4 + +L4:                                               ; preds = %L5, %bb2 +  %res.0 = phi i32 [ 385, %L5 ], [ 35, %bb2 ]     ; <i32> [#uses=1] +  br label %L3 + +L3:                                               ; preds = %L4, %bb2 +  %res.1 = phi i32 [ %res.0, %L4 ], [ 5, %bb2 ]   ; <i32> [#uses=1] +  br label %L2 + +L2:                                               ; preds = %L3, %bb2 +  %res.2 = phi i32 [ %res.1, %L3 ], [ 1, %bb2 ]   ; <i32> [#uses=1] +  %phitmp = mul i32 %res.2, 6                     ; <i32> [#uses=1] +  br label %L1 + +L1:                                               ; preds = %L2, %bb2 +  %res.3 = phi i32 [ %phitmp, %L2 ], [ 2, %bb2 ]  ; <i32> [#uses=1] +; CHECK: ldap r11, .LBA3_foo_L5 +; CHECK: stw r11, dp[nextaddr] +  store i8* blockaddress(@foo, %L5), i8** @nextaddr, align 4 +  ret i32 %res.3 +}  | 

