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| author | Andrew Trick <atrick@apple.com> | 2012-10-09 23:44:29 +0000 | 
|---|---|---|
| committer | Andrew Trick <atrick@apple.com> | 2012-10-09 23:44:29 +0000 | 
| commit | 3b8085db785f9e17c15cc7088603b36e4fe5f746 (patch) | |
| tree | 7cfda2bcd01928421042f9c0ff52323d2ec4f973 | |
| parent | cfcf5202a196dd36b0fe872d9d4f5c89df11dad1 (diff) | |
| download | bcm5719-llvm-3b8085db785f9e17c15cc7088603b36e4fe5f746.tar.gz bcm5719-llvm-3b8085db785f9e17c15cc7088603b36e4fe5f746.zip | |
misched: Doxument the TargetSchedule API.
llvm-svn: 165565
| -rw-r--r-- | llvm/include/llvm/CodeGen/TargetSchedule.h | 29 | 
1 files changed, 22 insertions, 7 deletions
| diff --git a/llvm/include/llvm/CodeGen/TargetSchedule.h b/llvm/include/llvm/CodeGen/TargetSchedule.h index ffcb793fc6b..6a5359de149 100644 --- a/llvm/include/llvm/CodeGen/TargetSchedule.h +++ b/llvm/include/llvm/CodeGen/TargetSchedule.h @@ -37,23 +37,35 @@ class TargetSchedModel {  public:    TargetSchedModel(): STI(0), TII(0) {} +  /// \brief Initialize the machine model for instruction scheduling. +  /// +  /// The machine model API keeps a copy of the top-level MCSchedModel table +  /// indices and may query TargetSubtargetInfo and TargetInstrInfo to resolve +  /// dynamic properties.    void init(const MCSchedModel &sm, const TargetSubtargetInfo *sti,              const TargetInstrInfo *tii); +  /// \brief TargetInstrInfo getter.    const TargetInstrInfo *getInstrInfo() const { return TII; } -  /// Return true if this machine model includes an instruction-level scheduling -  /// model. This is more detailed than the course grain IssueWidth and default +  /// \brief Return true if this machine model includes an instruction-level +  /// scheduling model. +  /// +  /// This is more detailed than the course grain IssueWidth and default    /// latency properties, but separate from the per-cycle itinerary data.    bool hasInstrSchedModel() const; -  /// Return true if this machine model includes cycle-to-cycle itinerary -  /// data. This models scheduling at each stage in the processor pipeline. +  /// \brief Return true if this machine model includes cycle-to-cycle itinerary +  /// data. +  /// +  /// This models scheduling at each stage in the processor pipeline.    bool hasInstrItineraries() const; -  /// computeOperandLatency - Compute and return the latency of the given data -  /// dependent def and use when the operand indices are already known. UseMI -  /// may be NULL for an unknown user. +  /// \brief Compute operand latency based on the available machine model. +  /// +  /// Computes and return the latency of the given data dependent def and use +  /// when the operand indices are already known. UseMI may be NULL for an +  /// unknown user.    ///    /// FindMin may be set to get the minimum vs. expected latency. Minimum    /// latency is used for scheduling groups, while expected latency is for @@ -62,7 +74,10 @@ public:                                   const MachineInstr *UseMI, unsigned UseOperIdx,                                   bool FindMin) const; +  /// \brief Identify the processor corresponding to the current subtarget.    unsigned getProcessorID() const { return SchedModel.getProcessorID(); } + +  /// \brief Maximum number of micro-ops that may be scheduled per cycle.    unsigned getIssueWidth() const { return SchedModel.IssueWidth; }  private: | 

