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authorBob Wilson <bob.wilson@apple.com>2009-10-13 20:50:28 +0000
committerBob Wilson <bob.wilson@apple.com>2009-10-13 20:50:28 +0000
commit3b51560ae4d08a10a9301c1a5d953a985ec3b01c (patch)
treee401d929ae322b720e2efe45caf8add0ed214d9d
parentfd04c74bc0f83966f26d9f62a98f3ea9eaa83fd1 (diff)
downloadbcm5719-llvm-3b51560ae4d08a10a9301c1a5d953a985ec3b01c.tar.gz
bcm5719-llvm-3b51560ae4d08a10a9301c1a5d953a985ec3b01c.zip
Revise ARM inline assembly memory operands to require the memory address to
be in a register. The previous use of ARM address mode 2 was completely arbitrary and inappropriate for Thumb. Radar 7137468. llvm-svn: 84022
-rw-r--r--llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp12
-rw-r--r--llvm/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp5
-rw-r--r--llvm/test/CodeGen/ARM/2009-05-18-InlineAsmMem.ll4
3 files changed, 11 insertions, 10 deletions
diff --git a/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp b/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
index b0b100c8efc..16518517618 100644
--- a/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
+++ b/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
@@ -2156,14 +2156,10 @@ bool ARMDAGToDAGISel::
SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode,
std::vector<SDValue> &OutOps) {
assert(ConstraintCode == 'm' && "unexpected asm memory constraint");
-
- SDValue Base, Offset, Opc;
- if (!SelectAddrMode2(Op, Op, Base, Offset, Opc))
- return true;
-
- OutOps.push_back(Base);
- OutOps.push_back(Offset);
- OutOps.push_back(Opc);
+ // Require the address to be in a register. That is safe for all ARM
+ // variants and it is hard to do anything much smarter without knowing
+ // how the operand is used.
+ OutOps.push_back(Op);
return false;
}
diff --git a/llvm/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp b/llvm/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp
index 1679e12be0e..546731b00d3 100644
--- a/llvm/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp
+++ b/llvm/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp
@@ -1017,7 +1017,10 @@ bool ARMAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
const char *ExtraCode) {
if (ExtraCode && ExtraCode[0])
return true; // Unknown modifier.
- printAddrMode2Operand(MI, OpNum);
+
+ const MachineOperand &MO = MI->getOperand(OpNum);
+ assert(MO.isReg() && "unexpected inline asm memory operand");
+ O << "[" << getRegisterName(MO.getReg()) << "]";
return false;
}
diff --git a/llvm/test/CodeGen/ARM/2009-05-18-InlineAsmMem.ll b/llvm/test/CodeGen/ARM/2009-05-18-InlineAsmMem.ll
index 2fc9eb37417..1e2707f7b5b 100644
--- a/llvm/test/CodeGen/ARM/2009-05-18-InlineAsmMem.ll
+++ b/llvm/test/CodeGen/ARM/2009-05-18-InlineAsmMem.ll
@@ -1,7 +1,9 @@
-; RUN: llc < %s -march=arm | grep swp
+; RUN: llc < %s -march=arm | FileCheck %s
+; RUN: llc < %s -march=thumb | FileCheck %s
; PR4091
define void @foo(i32 %i, i32* %p) nounwind {
+;CHECK: swp r2, r0, [r1]
%asmtmp = call i32 asm sideeffect "swp $0, $2, $3", "=&r,=*m,r,*m,~{memory}"(i32* %p, i32 %i, i32* %p) nounwind
ret void
}
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