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| author | Petar Jovanovic <petar.jovanovic@imgtec.com> | 2014-08-10 22:49:54 +0000 |
|---|---|---|
| committer | Petar Jovanovic <petar.jovanovic@imgtec.com> | 2014-08-10 22:49:54 +0000 |
| commit | 3a908a0bfc00605e6d7cd51406fcfe03251f624f (patch) | |
| tree | 4f91887f55b10b94bebce1e39a73be9d266f8dc3 | |
| parent | 399e99ae75832dd8179c00a167c1b0172bde0627 (diff) | |
| download | bcm5719-llvm-3a908a0bfc00605e6d7cd51406fcfe03251f624f.tar.gz bcm5719-llvm-3a908a0bfc00605e6d7cd51406fcfe03251f624f.zip | |
Add support for scalarizing cttz_zero_undef
Follow up to r214266. Add missing case in ScalarizeVectorResult() for
cttz_zero_undef.
Differential Revision: http://reviews.llvm.org/D4813
llvm-svn: 215330
| -rw-r--r-- | llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp | 1 | ||||
| -rw-r--r-- | llvm/test/CodeGen/Mips/cttz-v.ll | 37 |
2 files changed, 38 insertions, 0 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp index 9801781013a..8f4bce57a55 100644 --- a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp @@ -72,6 +72,7 @@ void DAGTypeLegalizer::ScalarizeVectorResult(SDNode *N, unsigned ResNo) { case ISD::CTLZ_ZERO_UNDEF: case ISD::CTPOP: case ISD::CTTZ: + case ISD::CTTZ_ZERO_UNDEF: case ISD::FABS: case ISD::FCEIL: case ISD::FCOS: diff --git a/llvm/test/CodeGen/Mips/cttz-v.ll b/llvm/test/CodeGen/Mips/cttz-v.ll new file mode 100644 index 00000000000..9470441da90 --- /dev/null +++ b/llvm/test/CodeGen/Mips/cttz-v.ll @@ -0,0 +1,37 @@ +; RUN: llc < %s -march=mipsel -mcpu=mips32r2 | FileCheck %s -check-prefix=MIPS32 +; RUN: llc < %s -march=mips64el -mcpu=mips64r2 | FileCheck %s -check-prefix=MIPS64 + +declare <2 x i32> @llvm.cttz.v2i32(<2 x i32>, i1) + +define <2 x i32> @cttzv2i32(<2 x i32> %x) { +entry: +; MIPS32-DAG: addiu $[[R0:[0-9]+]], $4, -1 +; MIPS32-DAG: not $[[R1:[0-9]+]], $4 +; MIPS32-DAG: and $[[R2:[0-9]+]], $[[R1]], $[[R0]] +; MIPS32-DAG: clz $[[R3:[0-9]+]], $[[R2]] +; MIPS32-DAG: addiu $[[R4:[0-9]+]], $zero, 32 +; MIPS32-DAG: subu $2, $[[R4]], $[[R3]] +; MIPS32-DAG: addiu $[[R5:[0-9]+]], $5, -1 +; MIPS32-DAG: not $[[R6:[0-9]+]], $5 +; MIPS32-DAG: and $[[R7:[0-9]+]], $[[R6]], $[[R5]] +; MIPS32-DAG: clz $[[R8:[0-9]+]], $[[R7]] +; MIPS32-DAG: jr $ra +; MIPS32-DAG: subu $3, $[[R4]], $[[R8]] + +; MIPS64-DAG: addiu $[[R0:[0-9]+]], $4, -1 +; MIPS64-DAG: not $[[R1:[0-9]+]], $4 +; MIPS64-DAG: and $[[R2:[0-9]+]], $[[R1]], $[[R0]] +; MIPS64-DAG: clz $[[R3:[0-9]+]], $[[R2]] +; MIPS64-DAG: addiu $[[R4:[0-9]+]], $zero, 32 +; MIPS64-DAG: subu $2, $[[R4]], $[[R3]] +; MIPS64-DAG: addiu $[[R5:[0-9]+]], $5, -1 +; MIPS64-DAG: not $[[R6:[0-9]+]], $5 +; MIPS64-DAG: and $[[R7:[0-9]+]], $[[R6]], $[[R5]] +; MIPS64-DAG: clz $[[R8:[0-9]+]], $[[R7]] +; MIPS64-DAG: jr $ra +; MIPS64-DAG: subu $3, $[[R4]], $[[R8]] + + %ret = call <2 x i32> @llvm.cttz.v2i32(<2 x i32> %x, i1 true) + ret <2 x i32> %ret +} + |
