[AArch64] Adjust the cost model for Exynos

Improve the modeling of ALU instructions.

llvm-svn: 350663

3 files changed, 58 insertions, 56 deletions

diff --git a/llvm/lib/Target/AArch64/AArch64SchedExynosM1.td b/llvm/lib/Target/AArch64/AArch64SchedExynosM1.td
index 7f1c2d4c764..f757d53b6c1 100644
--- a/llvm/lib/Target/AArch64/AArch64SchedExynosM1.td
+++ b/llvm/lib/Target/AArch64/AArch64SchedExynosM1.td
@@ -78,9 +78,8 @@ def M1WriteAC : SchedWriteRes<[M1UnitALU,
 def M1WriteAD : SchedWriteRes<[M1UnitALU,
                                M1UnitC]>   { let Latency = 2;
                                              let NumMicroOps = 2; }
-def M1WriteAX : SchedWriteVariant<[SchedVar<ExynosExtPred, [M1WriteA1]>,
-                                   SchedVar<NoSchedPred,   [M1WriteAA]>]>;
-def M1WriteAY : SchedWriteVariant<[SchedVar<ExynosShiftPred, [M1WriteA1]>,
+def M1WriteAX : SchedWriteVariant<[SchedVar<ExynosArithPred, [M1WriteA1]>,
+                                   SchedVar<ExynosLogicPred, [M1WriteA1]>,
                                    SchedVar<NoSchedPred,     [M1WriteAA]>]>;
 def M1WriteC1 : SchedWriteRes<[M1UnitC]>   { let Latency = 1; }
 def M1WriteC2 : SchedWriteRes<[M1UnitC]>   { let Latency = 2; }
@@ -430,7 +429,7 @@ def : InstRW<[M1WriteAD], (instregex "^TBN?Z[WX]")>;
 
 // Arithmetic and logical integer instructions.
 def : InstRW<[M1WriteAX], (instregex ".+rx(64)?$")>;
-def : InstRW<[M1WriteAY], (instregex ".+rs$")>;
+def : InstRW<[M1WriteAX], (instregex ".+rs$")>;
 
 // Move instructions.
 def : InstRW<[M1WriteCOPY], (instrs COPY)>;
diff --git a/llvm/lib/Target/AArch64/AArch64SchedExynosM3.td b/llvm/lib/Target/AArch64/AArch64SchedExynosM3.td
index 288a202c1df..15935088a17 100644
--- a/llvm/lib/Target/AArch64/AArch64SchedExynosM3.td
+++ b/llvm/lib/Target/AArch64/AArch64SchedExynosM3.td
@@ -127,18 +127,18 @@ def M3WriteAD : SchedWriteRes<[M3UnitALU,
 def M3WriteC1 : SchedWriteRes<[M3UnitC]>   { let Latency = 1; }
 def M3WriteC2 : SchedWriteRes<[M3UnitC]>   { let Latency = 2; }
 def M3WriteAU : SchedWriteVariant<[SchedVar<IsCopyIdiomPred, [M3WriteZ0]>,
-                                   SchedVar<ExynosShiftPred, [M3WriteA1]>,
+                                   SchedVar<ExynosArithPred, [M3WriteA1]>,
+                                   SchedVar<ExynosLogicPred, [M3WriteA1]>,
                                    SchedVar<NoSchedPred,     [M3WriteAA]>]>;
 def M3WriteAV : SchedWriteVariant<[SchedVar<IsCopyIdiomPred, [M3WriteZ0]>,
                                    SchedVar<NoSchedPred,     [M3WriteAA]>]>;
 def M3WriteAW : SchedWriteVariant<[SchedVar<IsZeroIdiomPred, [M3WriteZ0]>,
                                    SchedVar<NoSchedPred,     [M3WriteAA]>]>;
-def M3WriteAX : SchedWriteVariant<[SchedVar<ExynosExtPred, [M3WriteA1]>,
-                                   SchedVar<NoSchedPred,   [M3WriteAA]>]>;
+def M3WriteAX : SchedWriteVariant<[SchedVar<ExynosArithPred, [M3WriteA1]>,
+                                   SchedVar<ExynosLogicPred, [M3WriteA1]>,
+                                   SchedVar<NoSchedPred,     [M3WriteAA]>]>;
 def M3WriteAY : SchedWriteVariant<[SchedVar<ExynosRotateRightImmPred, [M3WriteA1]>,
                                    SchedVar<NoSchedPred,              [M3WriteAA]>]>;
-def M3WriteAZ : SchedWriteVariant<[SchedVar<ExynosShiftPred, [M3WriteA1]>,
-                                   SchedVar<NoSchedPred,     [M3WriteAA]>]>;
 
 def M3WriteB1 : SchedWriteRes<[M3UnitB]> { let Latency = 1; }
 def M3WriteBX : SchedWriteVariant<[SchedVar<ExynosBranchLinkLRPred, [M3WriteAC]>,
@@ -484,10 +484,10 @@ def : InstRW<[M3WriteC1], (instregex "^CBN?Z[WX]")>;
 def : InstRW<[M3WriteAD], (instregex "^TBN?Z[WX]")>;
 
 // Arithmetic and logical integer instructions.
-def : InstRW<[M3WriteAZ], (instregex "^(ADD|AND|BIC|EON|EOR|ORN|SUB)[WX]rs$")>;
+def : InstRW<[M3WriteAX], (instregex "^(ADD|AND|BIC|EON|EOR|ORN|SUB)[WX]rs$")>;
 def : InstRW<[M3WriteAU], (instrs ORRWrs, ORRXrs)>;
 def : InstRW<[M3WriteAX], (instregex "^(ADD|SUB)S?[WX]rx(64)?$")>;
-def : InstRW<[M3WriteAZ], (instregex "^(ADD|AND|BIC|SUB)S[WX]rs$")>;
+def : InstRW<[M3WriteAX], (instregex "^(ADD|AND|BIC|SUB)S[WX]rs$")>;
 def : InstRW<[M3WriteAV], (instrs ADDWri, ADDXri)>;
 def : InstRW<[M3WriteAW], (instrs ORRWri, ORRXri)>;
 
diff --git a/llvm/lib/Target/AArch64/AArch64SchedPredExynos.td b/llvm/lib/Target/AArch64/AArch64SchedPredExynos.td
index 998b0e21e96..2044e30ec1c 100644
--- a/llvm/lib/Target/AArch64/AArch64SchedPredExynos.td
+++ b/llvm/lib/Target/AArch64/AArch64SchedPredExynos.td
@@ -30,24 +30,52 @@ def ExynosBranchLinkLRPred : MCSchedPredicate<
                                CheckAll<[CheckOpcode<[BLR]>,
                                          CheckRegOperand<0, LR>]>>;
 
-// Identify arithmetic and logic instructions without or with limited extension.
-def ExynosExtFn   : TIIPredicate<
-                      "isExynosExtFast",
-                      MCOpcodeSwitchStatement<
-                        [MCOpcodeSwitchCase<
-                           IsArithExtOp.ValidOpcodes,
-                           MCReturnStatement<
-                             CheckAny<[CheckExtBy0,
-                                       CheckAll<
-                                         [CheckAny<
-                                           [CheckExtUXTW,
-                                            CheckExtUXTX]>,
-                                          CheckAny<
-                                            [CheckExtBy1,
-                                             CheckExtBy2,
-                                             CheckExtBy3]>]>]>>>],
-                        MCReturnStatement<FalsePred>>>;
-def ExynosExtPred : MCSchedPredicate<ExynosExtFn>;
+// Identify arithmetic instructions without or with limited extension or shift.
+def ExynosArithFn   : TIIPredicate<
+                        "isExynosArithFast",
+                        MCOpcodeSwitchStatement<
+                          [MCOpcodeSwitchCase<
+                             IsArithExtOp.ValidOpcodes,
+                             MCReturnStatement<
+                               CheckAny<[CheckExtBy0,
+                                         CheckAll<
+                                           [CheckAny<
+                                             [CheckExtUXTW,
+                                              CheckExtUXTX]>,
+                                            CheckAny<
+                                              [CheckExtBy1,
+                                               CheckExtBy2,
+                                               CheckExtBy3]>]>]>>>,
+                           MCOpcodeSwitchCase<
+                             IsArithShiftOp.ValidOpcodes,
+                             MCReturnStatement<ExynosCheckShift>>],
+                          MCReturnStatement<FalsePred>>>;
+def ExynosArithPred : MCSchedPredicate<ExynosArithFn>;
+
+// Identify logic instructions with limited shift.
+def ExynosLogicFn   : TIIPredicate<
+                        "isExynosLogicFast",
+                        MCOpcodeSwitchStatement<
+                          [MCOpcodeSwitchCase<
+                             IsLogicShiftOp.ValidOpcodes,
+                             MCReturnStatement<ExynosCheckShift>>],
+                          MCReturnStatement<FalsePred>>>;
+def ExynosLogicPred : MCSchedPredicate<ExynosLogicFn>;
+
+// Identify more logic instructions with limited shift.
+def ExynosLogicExFn   : TIIPredicate<
+                          "isExynosLogicExFast",
+                          MCOpcodeSwitchStatement<
+                            [MCOpcodeSwitchCase<
+                               IsLogicShiftOp.ValidOpcodes,
+                               MCReturnStatement<
+                                 CheckAny<
+                                   [ExynosCheckShift,
+                                    CheckAll<
+                                     [CheckShiftLSL,
+                                      CheckShiftBy8]>]>>>],
+                            MCReturnStatement<FalsePred>>>;
+def ExynosLogicExPred : MCSchedPredicate<ExynosLogicExFn>;
 
 // Identify a load or store using the register offset addressing mode
 // with a scaled non-extended register.
@@ -108,32 +136,7 @@ def ExynosRotateRightImmPred : MCSchedPredicate<
                                  CheckAll<[CheckOpcode<[EXTRWrri, EXTRXrri]>,
                                            CheckSameRegOperand<1, 2>]>>;
 
-// Identify arithmetic and logic instructions with limited shift.
-def ExynosShiftFn   : TIIPredicate<
-                        "isExynosShiftFast",
-                        MCOpcodeSwitchStatement<
-                          [MCOpcodeSwitchCase<
-                             IsArithLogicShiftOp.ValidOpcodes,
-                             MCReturnStatement<ExynosCheckShift>>],
-                          MCReturnStatement<FalsePred>>>;
-def ExynosShiftPred : MCSchedPredicate<ExynosShiftFn>;
-
-// Identify more arithmetic and logic instructions with limited shift.
-def ExynosShiftExFn   : TIIPredicate<
-                          "isExynosShiftExFast",
-                          MCOpcodeSwitchStatement<
-                            [MCOpcodeSwitchCase<
-                               IsArithLogicShiftOp.ValidOpcodes,
-                               MCReturnStatement<
-                                 CheckAny<
-                                   [ExynosCheckShift,
-                                    CheckAll<
-                                     [CheckShiftLSL,
-                                      CheckShiftBy8]>]>>>],
-                            MCReturnStatement<FalsePred>>>;
-def ExynosShiftExPred : MCSchedPredicate<ExynosShiftExFn>;
-
-// Identify arithmetic and logic immediate instructions.
+// Identify cheap arithmetic and logic immediate instructions.
 def ExynosCheapFn : TIIPredicate<
                       "isExynosCheapAsMove",
                       MCOpcodeSwitchStatement<
@@ -142,4 +145,4 @@ def ExynosCheapFn : TIIPredicate<
                            MCReturnStatement<TruePred>>],
                         MCReturnStatement<
                           CheckAny<
-                            [ExynosExtFn, ExynosResetFn, ExynosShiftFn]>>>>;
+                            [ExynosArithFn, ExynosResetFn, ExynosLogicFn]>>>>;