[AArch64] Avoid materializing constant 1 by using csinc, rather than csel.

This is similar to what was done in r261675, but for CSINC rather than CSINV.

Differential Revision: https://reviews.llvm.org/D23892

llvm-svn: 279822

3 files changed, 52 insertions, 6 deletions

diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.td b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
index ad6c628ab93..9c77b58e273 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
@@ -1133,6 +1133,14 @@ def : Pat<(AArch64csel (i32 0), (i32 1), (i32 imm:$cc), NZCV),
           (CSINCWr WZR, WZR, (i32 imm:$cc))>;
 def : Pat<(AArch64csel (i64 0), (i64 1), (i32 imm:$cc), NZCV),
           (CSINCXr XZR, XZR, (i32 imm:$cc))>;
+def : Pat<(AArch64csel GPR32:$tval, (i32 1), (i32 imm:$cc), NZCV),
+          (CSINCWr GPR32:$tval, WZR, (i32 imm:$cc))>;
+def : Pat<(AArch64csel GPR64:$tval, (i64 1), (i32 imm:$cc), NZCV),
+          (CSINCXr GPR64:$tval, XZR, (i32 imm:$cc))>;
+def : Pat<(AArch64csel (i32 1), GPR32:$fval, (i32 imm:$cc), NZCV),
+          (CSINCWr GPR32:$fval, WZR, (i32 (inv_cond_XFORM imm:$cc)))>;
+def : Pat<(AArch64csel (i64 1), GPR64:$fval, (i32 imm:$cc), NZCV),
+          (CSINCXr GPR64:$fval, XZR, (i32 (inv_cond_XFORM imm:$cc)))>;
 def : Pat<(AArch64csel (i32 0), (i32 -1), (i32 imm:$cc), NZCV),
           (CSINVWr WZR, WZR, (i32 imm:$cc))>;
 def : Pat<(AArch64csel (i64 0), (i64 -1), (i32 imm:$cc), NZCV),
diff --git a/llvm/test/CodeGen/AArch64/arm64-csel.ll b/llvm/test/CodeGen/AArch64/arm64-csel.ll
index 98eba30f119..3e246105f05 100644
--- a/llvm/test/CodeGen/AArch64/arm64-csel.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-csel.ll
@@ -228,3 +228,43 @@ entry:
   %inc.c = add i64 %inc, %c
   ret i64 %inc.c
 }
+
+define i32 @foo20(i32 %x) {
+; CHECK-LABEL: foo20:
+; CHECK: cmp w0, #5
+; CHECK: orr w[[REG:[0-9]+]], wzr, #0x6
+; CHECK: csinc w0, w[[REG]], wzr, eq
+  %cmp = icmp eq i32 %x, 5
+  %res = select i1 %cmp, i32 6, i32 1
+  ret i32 %res
+}
+
+define i64 @foo21(i64 %x) {
+; CHECK-LABEL: foo21:
+; CHECK: cmp x0, #5
+; CHECK: orr w[[REG:[0-9]+]], wzr, #0x6
+; CHECK: csinc x0, x[[REG]], xzr, eq
+  %cmp = icmp eq i64 %x, 5
+  %res = select i1 %cmp, i64 6, i64 1
+  ret i64 %res
+}
+
+define i32 @foo22(i32 %x) {
+; CHECK-LABEL: foo22:
+; CHECK: cmp w0, #5
+; CHECK: orr w[[REG:[0-9]+]], wzr, #0x6
+; CHECK: csinc w0, w[[REG]], wzr, ne
+  %cmp = icmp eq i32 %x, 5
+  %res = select i1 %cmp, i32 1, i32 6
+  ret i32 %res
+}
+
+define i64 @foo23(i64 %x) {
+; CHECK-LABEL: foo23:
+; CHECK: cmp x0, #5
+; CHECK: orr w[[REG:[0-9]+]], wzr, #0x6
+; CHECK: csinc x0, x[[REG]], xzr, ne
+  %cmp = icmp eq i64 %x, 5
+  %res = select i1 %cmp, i64 1, i64 6
+  ret i64 %res
+}
diff --git a/llvm/test/CodeGen/AArch64/f16-instructions.ll b/llvm/test/CodeGen/AArch64/f16-instructions.ll
index f50504a9a26..613c71a558b 100644
--- a/llvm/test/CodeGen/AArch64/f16-instructions.ll
+++ b/llvm/test/CodeGen/AArch64/f16-instructions.ll
@@ -185,9 +185,8 @@ define i1 @test_fcmp_une(half %a, half %b) #0 {
 ; CHECK-NEXT: fcvt s1, h1
 ; CHECK-NEXT: fcvt s0, h0
 ; CHECK-NEXT: fcmp s0, s1
-; CHECK-NEXT: orr [[TRUE:w[0-9]+]], wzr, #0x1
-; CHECK-NEXT: csel [[CC:w[0-9]+]], [[TRUE]], wzr, eq
-; CHECK-NEXT: csel w0, [[TRUE]], [[CC]], vs
+; CHECK-NEXT: cset [[TRUE:w[0-9]+]], eq
+; CHECK-NEXT: csinc w0, [[TRUE]], wzr, vc
 ; CHECK-NEXT: ret
 define i1 @test_fcmp_ueq(half %a, half %b) #0 {
   %r = fcmp ueq half %a, %b
@@ -254,9 +253,8 @@ define i1 @test_fcmp_uno(half %a, half %b) #0 {
 ; CHECK-NEXT: fcvt s1, h1
 ; CHECK-NEXT: fcvt s0, h0
 ; CHECK-NEXT: fcmp s0, s1
-; CHECK-NEXT: orr [[TRUE:w[0-9]+]], wzr, #0x1
-; CHECK-NEXT: csel [[CC:w[0-9]+]], [[TRUE]], wzr, mi
-; CHECK-NEXT: csel w0, [[TRUE]], [[CC]], gt
+; CHECK-NEXT: cset [[TRUE:w[0-9]+]], mi
+; CHECK-NEXT: csinc w0, [[TRUE]], wzr, le
 ; CHECK-NEXT: ret
 define i1 @test_fcmp_one(half %a, half %b) #0 {
   %r = fcmp one half %a, %b