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| author | Craig Topper <craig.topper@intel.com> | 2019-09-26 23:22:15 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@intel.com> | 2019-09-26 23:22:15 +0000 |
| commit | 3912ecb649c751399d07d8d61b3f1e0ff9455564 (patch) | |
| tree | f44845e78403d7833b1623c04398eb8d5b94bf38 | |
| parent | c2cc6817fa70eebddc84f09756f1ced3fdd1de81 (diff) | |
| download | bcm5719-llvm-3912ecb649c751399d07d8d61b3f1e0ff9455564.tar.gz bcm5719-llvm-3912ecb649c751399d07d8d61b3f1e0ff9455564.zip | |
[X86] Remove CodeGenOnly instructions added in r373021, but keep the isel patterns and add COPY_TO_REGCLASS to them.
llvm-svn: 373031
| -rw-r--r-- | llvm/lib/Target/X86/X86InstrAVX512.td | 26 |
1 files changed, 10 insertions, 16 deletions
diff --git a/llvm/lib/Target/X86/X86InstrAVX512.td b/llvm/lib/Target/X86/X86InstrAVX512.td index f9836067214..4d0a9cd2f3b 100644 --- a/llvm/lib/Target/X86/X86InstrAVX512.td +++ b/llvm/lib/Target/X86/X86InstrAVX512.td @@ -3958,18 +3958,6 @@ multiclass avx512_move_scalar<string asm, SDNode OpNode, PatFrag vzload_frag, !strconcat(asm, "\t{$src, $dst {${mask}} {z}|", "$dst {${mask}} {z}, $src}"), [], _.ExeDomain>, EVEX, EVEX_KZ, Sched<[WriteFLoad]>; - let isCodeGenOnly = 1 in { - def rmk_alt : AVX512PI<0x10, MRMSrcMem, (outs _.FRC:$dst), - (ins _.FRC:$src0, _.KRCWM:$mask, _.ScalarMemOp:$src), - !strconcat(asm, "\t{$src, $dst {${mask}}|", - "$dst {${mask}}, $src}"), - [], _.ExeDomain>, EVEX, EVEX_K, Sched<[WriteFLoad]>; - def rmkz_alt : AVX512PI<0x10, MRMSrcMem, (outs _.FRC:$dst), - (ins _.KRCWM:$mask, _.ScalarMemOp:$src), - !strconcat(asm, "\t{$src, $dst {${mask}} {z}|", - "$dst {${mask}} {z}, $src}"), - [], _.ExeDomain>, EVEX, EVEX_KZ, Sched<[WriteFLoad]>; - } } def mr: AVX512PI<0x11, MRMDestMem, (outs), (ins _.ScalarMemOp:$dst, _.FRC:$src), !strconcat(asm, "\t{$src, $dst|$dst, $src}"), @@ -4235,9 +4223,12 @@ def : Pat<(f32 (X86selects VK1WM:$mask, (f32 FR32X:$src1), fp32imm0)), (v4f32 (COPY_TO_REGCLASS FR32X:$src1, VR128X)))), FR32X)>; def : Pat<(f32 (X86selects VK1WM:$mask, (loadf32 addr:$src), (f32 FR32X:$src0))), - (VMOVSSZrmk_alt FR32X:$src0, VK1WM:$mask, addr:$src)>; + (COPY_TO_REGCLASS + (v4f32 (VMOVSSZrmk (v4f32 (COPY_TO_REGCLASS FR32X:$src0, VR128X)), + VK1WM:$mask, addr:$src)), + FR32X)>; def : Pat<(f32 (X86selects VK1WM:$mask, (loadf32 addr:$src), fp32imm0)), - (VMOVSSZrmkz_alt VK1WM:$mask, addr:$src)>; + (COPY_TO_REGCLASS (v4f32 (VMOVSSZrmkz VK1WM:$mask, addr:$src)), FR32X)>; def : Pat<(f64 (X86selects VK1WM:$mask, (f64 FR64X:$src1), (f64 FR64X:$src2))), (COPY_TO_REGCLASS (v2f64 (VMOVSDZrrk @@ -4250,9 +4241,12 @@ def : Pat<(f64 (X86selects VK1WM:$mask, (f64 FR64X:$src1), fp64imm0)), (v2f64 (COPY_TO_REGCLASS FR64X:$src1, VR128X)))), FR64X)>; def : Pat<(f64 (X86selects VK1WM:$mask, (loadf64 addr:$src), (f64 FR64X:$src0))), - (VMOVSDZrmk_alt FR64X:$src0, VK1WM:$mask, addr:$src)>; + (COPY_TO_REGCLASS + (v2f64 (VMOVSDZrmk (v2f64 (COPY_TO_REGCLASS FR64X:$src0, VR128X)), + VK1WM:$mask, addr:$src)), + FR64X)>; def : Pat<(f64 (X86selects VK1WM:$mask, (loadf64 addr:$src), fp64imm0)), - (VMOVSDZrmkz_alt VK1WM:$mask, addr:$src)>; + (COPY_TO_REGCLASS (v2f64 (VMOVSDZrmkz VK1WM:$mask, addr:$src)), FR64X)>; let hasSideEffects = 0, isCodeGenOnly = 1, ForceDisassemble = 1 in { def VMOVSSZrr_REV: AVX512<0x11, MRMDestReg, (outs VR128X:$dst), |
