summaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
authorChris Lattner <sabre@nondot.org>2009-03-26 05:25:59 +0000
committerChris Lattner <sabre@nondot.org>2009-03-26 05:25:59 +0000
commit3871781c7be6894a8731f50f4620386a14bc1f11 (patch)
tree822208f205468e462b59ab6d86d687e4b786dbc6
parent984fac5f5f0af8cf43f2feb025aceee70664e5c4 (diff)
downloadbcm5719-llvm-3871781c7be6894a8731f50f4620386a14bc1f11.tar.gz
bcm5719-llvm-3871781c7be6894a8731f50f4620386a14bc1f11.zip
fix warning in -asserts build.
llvm-svn: 67736
-rw-r--r--llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp6
1 files changed, 2 insertions, 4 deletions
diff --git a/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp b/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
index 6647d79c2da..657fc29bc6f 100644
--- a/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
+++ b/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
@@ -1388,8 +1388,7 @@ void PPCRegisterInfo::emitEpilogue(MachineFunction &MF,
addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset());
} else if (RetOpcode == PPC::TCRETURNri) {
MBBI = prior(MBB.end());
- MachineOperand &JumpTarget = MBBI->getOperand(0);
- assert(JumpTarget.isReg() && "Expecting register operand.");
+ assert(MBBI->getOperand(0).isReg() && "Expecting register operand.");
BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBCTR));
} else if (RetOpcode == PPC::TCRETURNai) {
MBBI = prior(MBB.end());
@@ -1402,8 +1401,7 @@ void PPCRegisterInfo::emitEpilogue(MachineFunction &MF,
addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset());
} else if (RetOpcode == PPC::TCRETURNri8) {
MBBI = prior(MBB.end());
- MachineOperand &JumpTarget = MBBI->getOperand(0);
- assert(JumpTarget.isReg() && "Expecting register operand.");
+ assert(MBBI->getOperand(0).isReg() && "Expecting register operand.");
BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBCTR8));
} else if (RetOpcode == PPC::TCRETURNai8) {
MBBI = prior(MBB.end());
OpenPOWER on IntegriCloud