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author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2017-07-21 18:06:36 +0000 |
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committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2017-07-21 18:06:36 +0000 |
commit | 37a58e03c72df95398807aab8c44b95b91146705 (patch) | |
tree | 577037e214bbbfc0f7b679008d47ed5087cb2bdf | |
parent | 3ad0d01e9e7c71a9de714380f232b45d7c8147fe (diff) | |
download | bcm5719-llvm-37a58e03c72df95398807aab8c44b95b91146705.tar.gz bcm5719-llvm-37a58e03c72df95398807aab8c44b95b91146705.zip |
AMDGPU: Fix getMemOpBaseRegImmOfs for flat with offsets
llvm-svn: 308762
-rw-r--r-- | llvm/lib/Target/AMDGPU/SIInstrInfo.cpp | 16 |
1 files changed, 13 insertions, 3 deletions
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp index 7d4ba2c52da..6cce7ca4175 100644 --- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp +++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp @@ -305,9 +305,19 @@ bool SIInstrInfo::getMemOpBaseRegImmOfs(MachineInstr &LdSt, unsigned &BaseReg, } if (isFLAT(LdSt)) { - const MachineOperand *AddrReg = getNamedOperand(LdSt, AMDGPU::OpName::vaddr); - BaseReg = AddrReg->getReg(); - Offset = 0; + const MachineOperand *VAddr = getNamedOperand(LdSt, AMDGPU::OpName::vaddr); + if (VAddr) { + // Can't analyze 2 offsets. + if (getNamedOperand(LdSt, AMDGPU::OpName::saddr)) + return false; + + BaseReg = VAddr->getReg(); + } else { + // scratch instructions have either vaddr or saddr. + BaseReg = getNamedOperand(LdSt, AMDGPU::OpName::saddr)->getReg(); + } + + Offset = getNamedOperand(LdSt, AMDGPU::OpName::offset)->getImm(); return true; } |