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authorMatt Arsenault <Matthew.Arsenault@amd.com>2018-05-09 18:29:26 +0000
committerMatt Arsenault <Matthew.Arsenault@amd.com>2018-05-09 18:29:26 +0000
commit378f86998c56cf97ec4f8b0fc96d99e0eb30cf21 (patch)
tree75b7e823afb057d110eecc318d2f4303d625d797
parent4e548fe06f300d3c9e013bd12be61e6a3859d9a3 (diff)
downloadbcm5719-llvm-378f86998c56cf97ec4f8b0fc96d99e0eb30cf21.tar.gz
bcm5719-llvm-378f86998c56cf97ec4f8b0fc96d99e0eb30cf21.zip
AMDGPU: Stop special casing constant indexes of extract_vector_elt
The same result folds out of the dynamic expansion logic if the index is constant. llvm-svn: 331906
-rw-r--r--llvm/lib/Target/AMDGPU/SIISelLowering.cpp15
1 files changed, 0 insertions, 15 deletions
diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
index 312abcc04c9..29e59cecc82 100644
--- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
@@ -4201,21 +4201,6 @@ SDValue SITargetLowering::lowerEXTRACT_VECTOR_ELT(SDValue Op,
if (SDValue Combined = performExtractVectorEltCombine(Op.getNode(), DCI))
return Combined;
- if (const ConstantSDNode *CIdx = dyn_cast<ConstantSDNode>(Idx)) {
- SDValue Result = DAG.getNode(ISD::BITCAST, SL, MVT::i32, Vec);
-
- if (CIdx->getZExtValue() == 1) {
- Result = DAG.getNode(ISD::SRL, SL, MVT::i32, Result,
- DAG.getConstant(16, SL, MVT::i32));
- } else {
- assert(CIdx->getZExtValue() == 0);
- }
-
- if (ResultVT.bitsLT(MVT::i32))
- Result = DAG.getNode(ISD::TRUNCATE, SL, MVT::i16, Result);
- return DAG.getNode(ISD::BITCAST, SL, ResultVT, Result);
- }
-
SDValue Four = DAG.getConstant(4, SL, MVT::i32);
// Convert vector index to bit-index (* 16)
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