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| author | Daniel Sanders <daniel.sanders@imgtec.com> | 2015-07-13 09:24:21 +0000 |
|---|---|---|
| committer | Daniel Sanders <daniel.sanders@imgtec.com> | 2015-07-13 09:24:21 +0000 |
| commit | 3745e02b0c006f10752c42e4e0ff5b90e6f7e811 (patch) | |
| tree | bd21348a01d463af81a47ce2e5737c98a9ff616e | |
| parent | b34a080701942dc6e9ab3dac7e9eb220022bad46 (diff) | |
| download | bcm5719-llvm-3745e02b0c006f10752c42e4e0ff5b90e6f7e811.tar.gz bcm5719-llvm-3745e02b0c006f10752c42e4e0ff5b90e6f7e811.zip | |
[mips] Explained the 'w' modifier in the Inline Assembler documentation.
It exists for compatibility with GCC which requires it to print MSA registers
for the 'f' constraint. Although LLVM doesn't need it, the 'w' modifier should
still be used for portability between the two compilers.
llvm-svn: 242015
| -rw-r--r-- | llvm/docs/LangRef.rst | 7 |
1 files changed, 5 insertions, 2 deletions
diff --git a/llvm/docs/LangRef.rst b/llvm/docs/LangRef.rst index 48771c211c1..e7d6f67c939 100644 --- a/llvm/docs/LangRef.rst +++ b/llvm/docs/LangRef.rst @@ -3200,7 +3200,8 @@ MIPS: ``sc`` instruction on the given subtarget (details vary). - ``r``, ``d``, ``y``: A 32 or 64-bit GPR register. - ``f``: A 32 or 64-bit FPU register (``F0-F31``), or a 128-bit MSA register - (``W0-W31``). + (``W0-W31``). In the case of MSA registers, it is recommended to use the ``w`` + argument modifier for compatibility with GCC. - ``c``: A 32-bit or 64-bit GPR register suitable for indirect jump (always ``25``). - ``l``: The ``lo`` register, 32 or 64-bit. @@ -3409,7 +3410,9 @@ MIPS: second word of a double-word memory operand. (On a big-endian system, ``D`` is equivalent to ``L``, and on little-endian system, ``D`` is equivalent to ``M``.) -- ``w``: No effect. +- ``w``: No effect. Provided for compatibility with GCC which requires this + modifier in order to print MSA registers (``W0-W31``) with the ``f`` + constraint. NVPTX: |
