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| author | Vladimir Medic <Vladimir.Medic@imgtec.com> | 2013-07-18 09:28:35 +0000 |
|---|---|---|
| committer | Vladimir Medic <Vladimir.Medic@imgtec.com> | 2013-07-18 09:28:35 +0000 |
| commit | 3467b90786da7c928464e0093747e52f4b7366b2 (patch) | |
| tree | 4c9c0c3b8f7486d2f105ff23b6d214e68bd3e2bf | |
| parent | ad1fff9be7d6e421299f9af025620eb5c97dfe0c (diff) | |
| download | bcm5719-llvm-3467b90786da7c928464e0093747e52f4b7366b2.tar.gz bcm5719-llvm-3467b90786da7c928464e0093747e52f4b7366b2.zip | |
This patch extends mips register parsing methods to allow indexed register parsing. The corresponding test cases are added to the patch.
llvm-svn: 186567
| -rw-r--r-- | llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp | 12 | ||||
| -rw-r--r-- | llvm/test/MC/Mips/mips-fpu-instructions.s | 4 |
2 files changed, 16 insertions, 0 deletions
diff --git a/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp b/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp index de3c4fd7954..56a5dfdafbd 100644 --- a/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp +++ b/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp @@ -1268,6 +1268,18 @@ MipsAsmParser::parseRegs(SmallVectorImpl<MCParsedAsmOperand*> &Operands, // Set the proper register kind. MipsOperand* op = static_cast<MipsOperand*>(Operands.back()); op->setRegKind(Kind); + if ((Kind == MipsOperand::Kind_CPURegs) + && (getLexer().is(AsmToken::LParen))) { + // Check if it is indexed addressing operand. + Operands.push_back(MipsOperand::CreateToken("(", getLexer().getLoc())); + Parser.Lex(); // Eat the parenthesis. + if (parseRegs(Operands,RegKind) != MatchOperand_Success) + return MatchOperand_NoMatch; + if (getLexer().isNot(AsmToken::RParen)) + return MatchOperand_NoMatch; + Operands.push_back(MipsOperand::CreateToken(")", getLexer().getLoc())); + Parser.Lex(); + } return MatchOperand_Success; } return MatchOperand_NoMatch; diff --git a/llvm/test/MC/Mips/mips-fpu-instructions.s b/llvm/test/MC/Mips/mips-fpu-instructions.s index e515872f260..5ff31f3e493 100644 --- a/llvm/test/MC/Mips/mips-fpu-instructions.s +++ b/llvm/test/MC/Mips/mips-fpu-instructions.s @@ -158,6 +158,8 @@ # CHECK: mtc2 $9, $4, 5 # encoding: [0x05,0x20,0x89,0x48] # CHECK: movf $2, $1, $fcc0 # encoding: [0x01,0x10,0x20,0x00] # CHECK: movt $2, $1, $fcc0 # encoding: [0x01,0x10,0x21,0x00] +# CHECK: luxc1 $f0, $6($5) # encoding: [0x05,0x00,0xa6,0x4c] +# CHECK: suxc1 $f4, $24($5) # encoding: [0x0d,0x20,0xb8,0x4c] cfc1 $a2,$0 mfc1 $a2,$f7 @@ -179,3 +181,5 @@ mtc2 $9, $4, 5 movf $2, $1, $fcc0 movt $2, $1, $fcc0 + luxc1 $f0, $a2($a1) + suxc1 $f4, $t8($a1)
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