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| author | Tom Stellard <tstellar@redhat.com> | 2018-09-26 16:53:36 +0000 |
|---|---|---|
| committer | Tom Stellard <tstellar@redhat.com> | 2018-09-26 16:53:36 +0000 |
| commit | 344475fce536e2f2f88d5e3b0a7bde51a2149341 (patch) | |
| tree | 22546264465945f9cc7e7e1d7dc6d8b9ccb67614 | |
| parent | 6562bd9ee032fcf19907027f36ae7f87da0fcf80 (diff) | |
| download | bcm5719-llvm-344475fce536e2f2f88d5e3b0a7bde51a2149341.tar.gz bcm5719-llvm-344475fce536e2f2f88d5e3b0a7bde51a2149341.zip | |
AMDGPU/SI: Change predicate to isCIOnly for 32-bit imm s_buffer_load* patterns
Summary:
This is essentially NFC, because the complex pattern used for these patterns
will fail on non-CI, but this makes the pattern consistent with other CI
smrd patterns. It is also a performance improvement, because the pattern
will now fail earlier on non-CI.
Reviewers: arsenm, nhaehnle
Reviewed By: arsenm
Subscribers: kzhuravl, jvesely, wdng, yaxunl, dstuttard, tpr, t-tye, llvm-commits
Differential Revision: https://reviews.llvm.org/D52469
llvm-svn: 343125
| -rw-r--r-- | llvm/lib/Target/AMDGPU/SMInstructions.td | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/lib/Target/AMDGPU/SMInstructions.td b/llvm/lib/Target/AMDGPU/SMInstructions.td index bd983cd6f19..6037dcc0e79 100644 --- a/llvm/lib/Target/AMDGPU/SMInstructions.td +++ b/llvm/lib/Target/AMDGPU/SMInstructions.td @@ -777,7 +777,7 @@ def : SMRD_Pattern_ci <"S_LOAD_DWORDX16", v16i32>; class SMLoad_Pattern_ci <string Instr, ValueType vt> : GCNPat < (vt (SIsbuffer_load v4i32:$sbase, (SMRDBufferImm32 i32:$offset), i1:$glc)), (!cast<InstSI>(Instr) $sbase, $offset, (as_i1imm $glc))> { - let OtherPredicates = [isCI]; // should this be isCIOnly? + let OtherPredicates = [isCIOnly]; } def : SMLoad_Pattern_ci <"S_BUFFER_LOAD_DWORD_IMM_ci", i32>; |
