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| author | Quentin Colombet <qcolombet@apple.com> | 2014-08-18 17:55:32 +0000 |
|---|---|---|
| committer | Quentin Colombet <qcolombet@apple.com> | 2014-08-18 17:55:32 +0000 |
| commit | 33b0bf200d91f6f738f2bd742d75e2d95b54c607 (patch) | |
| tree | 5446ba08d8daa9238d9064f35a1d4fd0be046920 | |
| parent | 456c991fb48026e99eaeaa4cc4d31cd7c37c09a7 (diff) | |
| download | bcm5719-llvm-33b0bf200d91f6f738f2bd742d75e2d95b54c607.tar.gz bcm5719-llvm-33b0bf200d91f6f738f2bd742d75e2d95b54c607.zip | |
[X86][Haswell][SchedModel] Add architecture specific scheduling models.
Group: Floating Point x87 instructions.
Sub-group: Math instructions.
<rdar://problem/15607571>
llvm-svn: 215913
| -rw-r--r-- | llvm/lib/Target/X86/X86SchedHaswell.td | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/llvm/lib/Target/X86/X86SchedHaswell.td b/llvm/lib/Target/X86/X86SchedHaswell.td index ec408d13d17..4dda178d0b0 100644 --- a/llvm/lib/Target/X86/X86SchedHaswell.td +++ b/llvm/lib/Target/X86/X86SchedHaswell.td @@ -1175,4 +1175,20 @@ def WriteFRNDINT : SchedWriteRes<[]> { } def : InstRW<[WriteFRNDINT], (instregex "FRNDINT")>; +//-- Math instructions --// + +// FSCALE. +def WriteFSCALE : SchedWriteRes<[]> { + let Latency = 75; // 49-125 + let NumMicroOps = 50; // 25-75 +} +def : InstRW<[WriteFSCALE], (instregex "FSCALE")>; + +// FXTRACT. +def WriteFXTRACT : SchedWriteRes<[]> { + let Latency = 15; + let NumMicroOps = 17; +} +def : InstRW<[WriteFXTRACT], (instregex "FXTRACT")>; + } // SchedModel |
