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| author | Craig Topper <craig.topper@gmail.com> | 2016-07-31 20:19:53 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@gmail.com> | 2016-07-31 20:19:53 +0000 |
| commit | 338ec9a0cbf220400c1200372736c1b5eae1f1ea (patch) | |
| tree | 44d04e68cf6f68aea75e7d1191b27073e66ea271 | |
| parent | 2a6bbb8203e9c0b8c4aa1210117bab8fbba240fe (diff) | |
| download | bcm5719-llvm-338ec9a0cbf220400c1200372736c1b5eae1f1ea.tar.gz bcm5719-llvm-338ec9a0cbf220400c1200372736c1b5eae1f1ea.zip | |
[AVX512] Stop treating VR512 specially in getLoadStoreRegOpcode and use the regular switch which already tried to handle it, but was unreachable. This has the added benefit of enabling aligned loads/stores if the stack is aligned.
llvm-svn: 277302
| -rw-r--r-- | llvm/lib/Target/X86/X86InstrInfo.cpp | 4 | ||||
| -rw-r--r-- | llvm/test/CodeGen/X86/avx512-intel-ocl.ll | 8 |
2 files changed, 5 insertions, 7 deletions
diff --git a/llvm/lib/Target/X86/X86InstrInfo.cpp b/llvm/lib/Target/X86/X86InstrInfo.cpp index fc346cb7228..b6f6a98f0ab 100644 --- a/llvm/lib/Target/X86/X86InstrInfo.cpp +++ b/llvm/lib/Target/X86/X86InstrInfo.cpp @@ -4845,8 +4845,6 @@ static unsigned getLoadStoreRegOpcode(unsigned Reg, return load ? X86::VMOVSSZrm : X86::VMOVSSZmr; if (RC->getSize() == 8 && X86::FR64XRegClass.hasSubClassEq(RC)) return load ? X86::VMOVSDZrm : X86::VMOVSDZmr; - if (X86::VR512RegClass.hasSubClassEq(RC)) - return load ? X86::VMOVUPSZrm : X86::VMOVUPSZmr; } bool HasAVX = STI.hasAVX(); @@ -4924,7 +4922,7 @@ static unsigned getLoadStoreRegOpcode(unsigned Reg, return load ? X86::VMOVUPSZ256rm : X86::VMOVUPSZ256mr; case 64: assert(X86::VR512RegClass.hasSubClassEq(RC) && "Unknown 64-byte regclass"); - assert(STI.hasVLX() && "Using 512-bit register requires AVX512"); + assert(STI.hasAVX512() && "Using 512-bit register requires AVX512"); if (isStackAligned) return load ? X86::VMOVAPSZrm : X86::VMOVAPSZmr; else diff --git a/llvm/test/CodeGen/X86/avx512-intel-ocl.ll b/llvm/test/CodeGen/X86/avx512-intel-ocl.ll index 69e06f547ce..44658be9cfd 100644 --- a/llvm/test/CodeGen/X86/avx512-intel-ocl.ll +++ b/llvm/test/CodeGen/X86/avx512-intel-ocl.ll @@ -62,11 +62,11 @@ define <16 x float> @testf16_regs(<16 x float> %a, <16 x float> %b) nounwind { ; test calling conventions - prolog and epilog ; WIN64-LABEL: test_prolog_epilog -; WIN64: vmovups %zmm21, {{.*(%rbp).*}} # 64-byte Spill -; WIN64: vmovups %zmm6, {{.*(%rbp).*}} # 64-byte Spill +; WIN64: vmovaps %zmm21, {{.*(%rbp).*}} # 64-byte Spill +; WIN64: vmovaps %zmm6, {{.*(%rbp).*}} # 64-byte Spill ; WIN64: call -; WIN64: vmovups {{.*(%rbp).*}}, %zmm6 # 64-byte Reload -; WIN64: vmovups {{.*(%rbp).*}}, %zmm21 # 64-byte Reload +; WIN64: vmovaps {{.*(%rbp).*}}, %zmm6 # 64-byte Reload +; WIN64: vmovaps {{.*(%rbp).*}}, %zmm21 # 64-byte Reload ; X64-LABEL: test_prolog_epilog ; X64: kmovq %k7, {{.*}}(%rsp) ## 8-byte Spill |
