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| author | Igor Breger <igor.breger@intel.com> | 2017-07-11 08:04:51 +0000 |
|---|---|---|
| committer | Igor Breger <igor.breger@intel.com> | 2017-07-11 08:04:51 +0000 |
| commit | 324d3791f81860f3ce1a8e14b839f73ed1fbee53 (patch) | |
| tree | 053ede0cf90804b18ea042fda723a0628ebc4225 | |
| parent | 2779165d8cee46d1dfc8ad63e73b51839ed9c30f (diff) | |
| download | bcm5719-llvm-324d3791f81860f3ce1a8e14b839f73ed1fbee53.tar.gz bcm5719-llvm-324d3791f81860f3ce1a8e14b839f73ed1fbee53.zip | |
[GlobalISel][X86] Use correct AND instructions.
AND8ri8 not supported in 64bit.
llvm-svn: 307630
| -rw-r--r-- | llvm/lib/Target/X86/X86InstructionSelector.cpp | 2 | ||||
| -rw-r--r-- | llvm/test/CodeGen/X86/GlobalISel/select-ext.mir | 2 |
2 files changed, 2 insertions, 2 deletions
diff --git a/llvm/lib/Target/X86/X86InstructionSelector.cpp b/llvm/lib/Target/X86/X86InstructionSelector.cpp index e912ebcfc12..859d3288db8 100644 --- a/llvm/lib/Target/X86/X86InstructionSelector.cpp +++ b/llvm/lib/Target/X86/X86InstructionSelector.cpp @@ -642,7 +642,7 @@ bool X86InstructionSelector::selectZext(MachineInstr &I, unsigned AndOpc; if (DstTy == LLT::scalar(8)) - AndOpc = X86::AND8ri8; + AndOpc = X86::AND8ri; else if (DstTy == LLT::scalar(16)) AndOpc = X86::AND16ri8; else if (DstTy == LLT::scalar(32)) diff --git a/llvm/test/CodeGen/X86/GlobalISel/select-ext.mir b/llvm/test/CodeGen/X86/GlobalISel/select-ext.mir index d8d48f627a7..b6734e5aa2b 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/select-ext.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/select-ext.mir @@ -51,7 +51,7 @@ registers: - { id: 0, class: gpr, preferred-register: '' } - { id: 1, class: gpr, preferred-register: '' } # ALL: %0 = COPY %dil -# ALL-NEXT: %1 = AND8ri8 %0, 1, implicit-def %eflags +# ALL-NEXT: %1 = AND8ri %0, 1, implicit-def %eflags # ALL-NEXT: %al = COPY %1 # ALL-NEXT: RET 0, implicit %al body: | |
