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| author | Anton Korobeynikov <asl@math.spbu.ru> | 2010-04-07 18:22:03 +0000 |
|---|---|---|
| committer | Anton Korobeynikov <asl@math.spbu.ru> | 2010-04-07 18:22:03 +0000 |
| commit | 32457d6c5e3e42002d2bd4cc2f4213416328abc9 (patch) | |
| tree | 3d31921ad1741205c9ee1a4eeb646230e926e996 | |
| parent | d351104f1909f8115332816541688862b3d087df (diff) | |
| download | bcm5719-llvm-32457d6c5e3e42002d2bd4cc2f4213416328abc9.tar.gz bcm5719-llvm-32457d6c5e3e42002d2bd4cc2f4213416328abc9.zip | |
Add some crude itin approximation for VFP load / stores on A9
llvm-svn: 100671
| -rw-r--r-- | llvm/lib/Target/ARM/ARMScheduleV7.td | 54 |
1 files changed, 54 insertions, 0 deletions
diff --git a/llvm/lib/Target/ARM/ARMScheduleV7.td b/llvm/lib/Target/ARM/ARMScheduleV7.td index f413aaf1a52..2dc621791d7 100644 --- a/llvm/lib/Target/ARM/ARMScheduleV7.td +++ b/llvm/lib/Target/ARM/ARMScheduleV7.td @@ -804,6 +804,60 @@ def CortexA9Itineraries : ProcessorItineraries<[ InstrStage<2, [FU_DRegsN], 0, Reserved>, InstrStage<1, [FU_Pipe0, FU_Pipe1]>, InstrStage<1, [FU_NPipe]>], [1, 1, 1]>, + // + // Single-precision FP Load + // use FU_Issue to enforce the 1 load/store per cycle limit + InstrItinData<IIC_fpLoad32, [InstrStage<1, [FU_DRegsVFP], 0, Required>, + InstrStage<2, [FU_DRegsN], 0, Reserved>, + InstrStage<1, [FU_Issue], 0>, + InstrStage<1, [FU_Pipe0, FU_Pipe1]>, + InstrStage<1, [FU_LdSt0], 0>, + InstrStage<1, [FU_NPipe]>]>, + // + // Double-precision FP Load + // use FU_Issue to enforce the 1 load/store per cycle limit + InstrItinData<IIC_fpLoad64, [InstrStage<1, [FU_DRegsVFP], 0, Required>, + InstrStage<2, [FU_DRegsN], 0, Reserved>, + InstrStage<1, [FU_Issue], 0>, + InstrStage<1, [FU_Pipe0, FU_Pipe1]>, + InstrStage<1, [FU_LdSt0], 0>, + InstrStage<1, [FU_NPipe]>]>, + // + // FP Load Multiple + // use FU_Issue to enforce the 1 load/store per cycle limit + InstrItinData<IIC_fpLoadm, [InstrStage<1, [FU_DRegsVFP], 0, Required>, + InstrStage<2, [FU_DRegsN], 0, Reserved>, + InstrStage<1, [FU_Issue], 0>, + InstrStage<1, [FU_Pipe0, FU_Pipe1]>, + InstrStage<1, [FU_LdSt0], 0>, + InstrStage<1, [FU_NPipe]>]>, + // + // Single-precision FP Store + // use FU_Issue to enforce the 1 load/store per cycle limit + InstrItinData<IIC_fpStore32,[InstrStage<1, [FU_DRegsVFP], 0, Required>, + InstrStage<2, [FU_DRegsN], 0, Reserved>, + InstrStage<1, [FU_Issue], 0>, + InstrStage<1, [FU_Pipe0, FU_Pipe1]>, + InstrStage<1, [FU_LdSt0], 0>, + InstrStage<1, [FU_NPipe]>]>, + // + // Double-precision FP Store + // use FU_Issue to enforce the 1 load/store per cycle limit + InstrItinData<IIC_fpStore64,[InstrStage<1, [FU_DRegsVFP], 0, Required>, + InstrStage<2, [FU_DRegsN], 0, Reserved>, + InstrStage<1, [FU_Issue], 0>, + InstrStage<1, [FU_Pipe0, FU_Pipe1]>, + InstrStage<1, [FU_LdSt0], 0>, + InstrStage<1, [FU_NPipe]>]>, + // + // FP Store Multiple + // use FU_Issue to enforce the 1 load/store per cycle limit + InstrItinData<IIC_fpStorem, [InstrStage<1, [FU_DRegsVFP], 0, Required>, + InstrStage<2, [FU_DRegsN], 0, Reserved>, + InstrStage<1, [FU_Issue], 0>, + InstrStage<1, [FU_Pipe0, FU_Pipe1]>, + InstrStage<1, [FU_LdSt0], 0>, + InstrStage<1, [FU_NPipe]>]>, // NEON // Issue through integer pipeline, and execute in NEON unit. // FIXME: Neon pipeline and LdSt unit are multiplexed. |
