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authorHal Finkel <hfinkel@anl.gov>2012-04-01 20:08:17 +0000
committerHal Finkel <hfinkel@anl.gov>2012-04-01 20:08:17 +0000
commit322e41a9144493600bf4474132a36f015231379f (patch)
tree9df87e0baf65e1ec3fd487965d0a025181dd4de3
parent9032344c15248ff5ae4da0f01a7878498e267ba4 (diff)
downloadbcm5719-llvm-322e41a9144493600bf4474132a36f015231379f.tar.gz
bcm5719-llvm-322e41a9144493600bf4474132a36f015231379f.zip
Enable prefetch generation on PPC64.
llvm-svn: 153851
-rw-r--r--llvm/lib/Target/PowerPC/PPCISelLowering.cpp3
-rw-r--r--llvm/lib/Target/PowerPC/PPCInstrInfo.td3
-rw-r--r--llvm/test/CodeGen/PowerPC/ppc64-prefetch.ll15
3 files changed, 21 insertions, 0 deletions
diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
index 00f2dcc8dbf..96b7074aa02 100644
--- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -389,6 +389,9 @@ PPCTargetLowering::PPCTargetLowering(PPCTargetMachine &TM)
setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
}
+ if (TM.getSubtarget<PPCSubtarget>().has64BitSupport())
+ setOperationAction(ISD::PREFETCH, MVT::Other, Legal);
+
setOperationAction(ISD::ATOMIC_LOAD, MVT::i32, Expand);
setOperationAction(ISD::ATOMIC_STORE, MVT::i32, Expand);
diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.td b/llvm/lib/Target/PowerPC/PPCInstrInfo.td
index 3a6dbcaab37..748486c1ca2 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrInfo.td
+++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.td
@@ -545,6 +545,9 @@ def DCBZL : DCB_Form<1014, 1, (outs), (ins memrr:$dst),
"dcbzl $dst", LdStDCBF, [(int_ppc_dcbzl xoaddr:$dst)]>,
PPC970_DGroup_Single;
+def : Pat<(prefetch xoaddr:$dst, (i32 0), imm, (i32 1)),
+ (DCBT xoaddr:$dst)>;
+
// Atomic operations
let usesCustomInserter = 1 in {
let Defs = [CR0] in {
diff --git a/llvm/test/CodeGen/PowerPC/ppc64-prefetch.ll b/llvm/test/CodeGen/PowerPC/ppc64-prefetch.ll
new file mode 100644
index 00000000000..b2f37097f92
--- /dev/null
+++ b/llvm/test/CodeGen/PowerPC/ppc64-prefetch.ll
@@ -0,0 +1,15 @@
+target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64"
+target triple = "powerpc64-unknown-linux-gnu"
+; RUN: llc < %s | FileCheck %s
+
+define void @test1(i8* %a, ...) nounwind {
+entry:
+ call void @llvm.prefetch(i8* %a, i32 0, i32 3, i32 1)
+ ret void
+}
+
+declare void @llvm.prefetch(i8*, i32, i32, i32)
+
+; CHECK: @test1
+; CHECK: dcbt
+
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