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| author | Sanjay Patel <spatel@rotateright.com> | 2018-10-07 15:05:39 +0000 |
|---|---|---|
| committer | Sanjay Patel <spatel@rotateright.com> | 2018-10-07 15:05:39 +0000 |
| commit | 31a3f2aabaf832bca14ecfe6c409ca0618681ffc (patch) | |
| tree | d8bfac7a4e526e2f69308df83a381907892eace8 | |
| parent | 4a5ff88fdbd7d8646de3ec6ecfbc5fd1036dcb50 (diff) | |
| download | bcm5719-llvm-31a3f2aabaf832bca14ecfe6c409ca0618681ffc.tar.gz bcm5719-llvm-31a3f2aabaf832bca14ecfe6c409ca0618681ffc.zip | |
[x86] add tests for FP logic folding for vectors with undefs; NFC
llvm-svn: 343938
| -rw-r--r-- | llvm/test/CodeGen/X86/fp-logic.ll | 26 |
1 files changed, 26 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/X86/fp-logic.ll b/llvm/test/CodeGen/X86/fp-logic.ll index 66362714a56..59dbe7adb16 100644 --- a/llvm/test/CodeGen/X86/fp-logic.ll +++ b/llvm/test/CodeGen/X86/fp-logic.ll @@ -320,6 +320,19 @@ define <4 x float> @fadd_bitcast_fneg_vec(<4 x float> %x, <4 x float> %y) { ret <4 x float> %fadd } +define <4 x float> @fadd_bitcast_fneg_vec_undef_elts(<4 x float> %x, <4 x float> %y) { +; CHECK-LABEL: fadd_bitcast_fneg_vec_undef_elts: +; CHECK: # %bb.0: +; CHECK-NEXT: xorps {{.*}}(%rip), %xmm1 +; CHECK-NEXT: addps %xmm1, %xmm0 +; CHECK-NEXT: retq + %bc1 = bitcast <4 x float> %y to <4 x i32> + %xor = xor <4 x i32> %bc1, <i32 2147483648, i32 2147483648, i32 undef, i32 2147483648> + %bc2 = bitcast <4 x i32> %xor to <4 x float> + %fadd = fadd <4 x float> %x, %bc2 + ret <4 x float> %fadd +} + define <4 x float> @fsub_bitcast_fneg_vec(<4 x float> %x, <4 x float> %y) { ; CHECK-LABEL: fsub_bitcast_fneg_vec: ; CHECK: # %bb.0: @@ -332,6 +345,19 @@ define <4 x float> @fsub_bitcast_fneg_vec(<4 x float> %x, <4 x float> %y) { ret <4 x float> %fsub } +define <4 x float> @fsub_bitcast_fneg_vec_elts(<4 x float> %x, <4 x float> %y) { +; CHECK-LABEL: fsub_bitcast_fneg_vec_elts: +; CHECK: # %bb.0: +; CHECK-NEXT: xorps {{.*}}(%rip), %xmm1 +; CHECK-NEXT: subps %xmm1, %xmm0 +; CHECK-NEXT: retq + %bc1 = bitcast <4 x float> %y to <4 x i32> + %xor = xor <4 x i32> %bc1, <i32 undef, i32 2147483648, i32 undef, i32 2147483648> + %bc2 = bitcast <4 x i32> %xor to <4 x float> + %fsub = fsub <4 x float> %x, %bc2 + ret <4 x float> %fsub +} + define <4 x float> @fadd_bitcast_fneg_vec_width(<4 x float> %x, <4 x float> %y) { ; CHECK-LABEL: fadd_bitcast_fneg_vec_width: ; CHECK: # %bb.0: |
