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authorQuentin Colombet <qcolombet@apple.com>2016-05-09 19:50:30 +0000
committerQuentin Colombet <qcolombet@apple.com>2016-05-09 19:50:30 +0000
commit3126db6fd7c3ac2e1e7c5308bca930422627d199 (patch)
tree80b07969f0f330b192469bf11b4a474a17abdd63
parent0c0ada01b6e0dc5565dc50ecf8aa82412c1dd902 (diff)
downloadbcm5719-llvm-3126db6fd7c3ac2e1e7c5308bca930422627d199.tar.gz
bcm5719-llvm-3126db6fd7c3ac2e1e7c5308bca930422627d199.zip
[X86] Drop the 64-bit alignment for LOW32_ADDR_ACCESS register class.
The only 64-bit register in that register class is RIP and it will not get spilled in the current ABIs. llvm-svn: 268963
-rw-r--r--llvm/lib/Target/X86/X86RegisterInfo.td5
1 files changed, 3 insertions, 2 deletions
diff --git a/llvm/lib/Target/X86/X86RegisterInfo.td b/llvm/lib/Target/X86/X86RegisterInfo.td
index 797ff4f2e8e..29ce2860537 100644
--- a/llvm/lib/Target/X86/X86RegisterInfo.td
+++ b/llvm/lib/Target/X86/X86RegisterInfo.td
@@ -421,11 +421,12 @@ def GR64_NOREX_NOSP : RegisterClass<"X86", [i64], 64,
// In such cases, it is fine to use RIP as we are sure the 32 high
// bits are not set. We do not need variants for NOSP as RIP is not
// allowed there.
-// Alignment is 64 because we have RIP.
+// RIP is not spilled anywhere for now, so stick to 32-bit alignment
+// to save on memory space.
// FIXME: We could allow all 64bit registers, but we would need
// something to check that the 32 high bits are not set,
// which we do not have right now.
-def LOW32_ADDR_ACCESS : RegisterClass<"X86", [i32], 64, (add GR32, RIP)>;
+def LOW32_ADDR_ACCESS : RegisterClass<"X86", [i32], 32, (add GR32, RIP)>;
// When RBP is used as a base pointer in a 32-bit addresses environement,
// this is also safe to use the full register to access addresses.
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