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| author | Jack Carter <jack.carter@imgtec.com> | 2013-03-28 23:45:13 +0000 |
|---|---|---|
| committer | Jack Carter <jack.carter@imgtec.com> | 2013-03-28 23:45:13 +0000 |
| commit | 311246c6d51a99439172ddf2cea28be4f53df4dd (patch) | |
| tree | 4abd935dfdb8c6df6973396388dc1323ed354505 | |
| parent | 3faf47c46225b0f56c14235550d363ae90f4f1c6 (diff) | |
| download | bcm5719-llvm-311246c6d51a99439172ddf2cea28be4f53df4dd.tar.gz bcm5719-llvm-311246c6d51a99439172ddf2cea28be4f53df4dd.zip | |
[Mips Assembler] Add support for OR macro with imediate opperand
Mips assembler supports macros that allows the OR instruction
to have an immediate parameter. This patch adds an instruction
alias that converts this macro into a Mips ORI instruction.
Contributer: Vladimir Medic
llvm-svn: 178316
| -rw-r--r-- | llvm/lib/Target/Mips/Mips64InstrInfo.td | 4 | ||||
| -rw-r--r-- | llvm/lib/Target/Mips/MipsInstrInfo.td | 3 | ||||
| -rw-r--r-- | llvm/test/MC/Mips/mips-alu-instructions.s | 2 |
3 files changed, 8 insertions, 1 deletions
diff --git a/llvm/lib/Target/Mips/Mips64InstrInfo.td b/llvm/lib/Target/Mips/Mips64InstrInfo.td index 1d5912a0354..dafa37558bb 100644 --- a/llvm/lib/Target/Mips/Mips64InstrInfo.td +++ b/llvm/lib/Target/Mips/Mips64InstrInfo.td @@ -342,7 +342,9 @@ def : InstAlias<"daddu $rs, $rt, $imm", def : InstAlias<"dadd $rs, $rt, $imm", (DADDi CPU64RegsOpnd:$rs, CPU64RegsOpnd:$rt, simm16_64:$imm), 1>; - +def : InstAlias<"or $rs, $rt, $imm", + (ORi64 CPU64RegsOpnd:$rs, CPU64RegsOpnd:$rt, uimm16_64:$imm), + 1>, Requires<[HasMips64]>; /// Move between CPU and coprocessor registers let DecoderNamespace = "Mips64" in { diff --git a/llvm/lib/Target/Mips/MipsInstrInfo.td b/llvm/lib/Target/Mips/MipsInstrInfo.td index 1c523d5bd83..043077fde04 100644 --- a/llvm/lib/Target/Mips/MipsInstrInfo.td +++ b/llvm/lib/Target/Mips/MipsInstrInfo.td @@ -1015,6 +1015,9 @@ def : InstAlias<"slt $rs, $rt, $imm", def : InstAlias<"xor $rs, $rt, $imm", (XORi CPURegsOpnd:$rs, CPURegsOpnd:$rt, simm16:$imm), 0>, Requires<[NotMips64]>; +def : InstAlias<"or $rs, $rt, $imm", + (ORi CPURegsOpnd:$rs, CPURegsOpnd:$rt, simm16:$imm), 0>, + Requires<[NotMips64]>; def : InstAlias<"nop", (SLL ZERO, ZERO, 0), 1>; def : InstAlias<"mfc0 $rt, $rd", (MFC0_3OP CPURegsOpnd:$rt, CPURegsOpnd:$rd, 0), 0>; diff --git a/llvm/test/MC/Mips/mips-alu-instructions.s b/llvm/test/MC/Mips/mips-alu-instructions.s index 816138ec654..7384d19e440 100644 --- a/llvm/test/MC/Mips/mips-alu-instructions.s +++ b/llvm/test/MC/Mips/mips-alu-instructions.s @@ -13,6 +13,7 @@ # CHECK: ins $19, $9, 6, 7 # encoding: [0x84,0x61,0x33,0x7d] # CHECK: nor $9, $6, $7 # encoding: [0x27,0x48,0xc7,0x00] # CHECK: or $3, $3, $5 # encoding: [0x25,0x18,0x65,0x00] +# CHECK: ori $4, $5, 17767 # encoding: [0x67,0x45,0xa4,0x34] # CHECK: ori $9, $6, 17767 # encoding: [0x67,0x45,0xc9,0x34] # CHECK: rotr $9, $6, 7 # encoding: [0xc2,0x49,0x26,0x00] # CHECK: rotrv $9, $6, $7 # encoding: [0x46,0x48,0xe6,0x00] @@ -40,6 +41,7 @@ ins $19, $9, 6,7 nor $9, $6, $7 or $3, $3, $5 + or $4, $5, 17767 ori $9, $6, 17767 rotr $9, $6, 7 rotrv $9, $6, $7 |
