diff options
| author | Jim Grosbach <grosbach@apple.com> | 2010-12-01 21:09:40 +0000 |
|---|---|---|
| committer | Jim Grosbach <grosbach@apple.com> | 2010-12-01 21:09:40 +0000 |
| commit | 30eb6c7e7100bb5b9a41d792cda0a30c65ca9655 (patch) | |
| tree | 0ee225f14f4093b413ca03d7e635c2293df22794 | |
| parent | 5fe5f453524b1db86c2e53adb9614d9aaff409ac (diff) | |
| download | bcm5719-llvm-30eb6c7e7100bb5b9a41d792cda0a30c65ca9655.tar.gz bcm5719-llvm-30eb6c7e7100bb5b9a41d792cda0a30c65ca9655.zip | |
Use the correct fixup type for ARM VLDR*
llvm-svn: 120604
| -rw-r--r-- | llvm/lib/Target/ARM/ARMMCCodeEmitter.cpp | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/llvm/lib/Target/ARM/ARMMCCodeEmitter.cpp b/llvm/lib/Target/ARM/ARMMCCodeEmitter.cpp index d35a1c6fb33..7a7864f75ef 100644 --- a/llvm/lib/Target/ARM/ARMMCCodeEmitter.cpp +++ b/llvm/lib/Target/ARM/ARMMCCodeEmitter.cpp @@ -658,7 +658,7 @@ getAddrModeS1OpValue(const MCInst &MI, unsigned OpIdx, return getAddrModeSOpValue(MI, OpIdx, 1); } -/// getAddrMode5OpValue - Return encoding info for 'reg +/- imm12' operand. +/// getAddrMode5OpValue - Return encoding info for 'reg +/- imm10' operand. uint32_t ARMMCCodeEmitter:: getAddrMode5OpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups) const { @@ -676,7 +676,7 @@ getAddrMode5OpValue(const MCInst &MI, unsigned OpIdx, assert(MO.isExpr() && "Unexpected machine operand type!"); const MCExpr *Expr = MO.getExpr(); - MCFixupKind Kind = MCFixupKind(ARM::fixup_arm_pcrel_12); + MCFixupKind Kind = MCFixupKind(ARM::fixup_arm_pcrel_10); Fixups.push_back(MCFixup::Create(0, Expr, Kind)); ++MCNumCPRelocations; |
