summaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
authorJim Grosbach <grosbach@apple.com>2011-07-13 22:26:58 +0000
committerJim Grosbach <grosbach@apple.com>2011-07-13 22:26:58 +0000
commit307de018675fa1b96a43fc264aaeaf4aaf5a16ff (patch)
tree420b653ca6248b06f034d8187f5bbbabac939230
parent9908c176669ea0d1c673541bfcf680a552464a61 (diff)
downloadbcm5719-llvm-307de018675fa1b96a43fc264aaeaf4aaf5a16ff.tar.gz
bcm5719-llvm-307de018675fa1b96a43fc264aaeaf4aaf5a16ff.zip
ARM parsing and encoding tests for CMN/CMP.
llvm-svn: 135098
-rw-r--r--llvm/test/MC/ARM/basic-arm-instructions.s59
1 files changed, 59 insertions, 0 deletions
diff --git a/llvm/test/MC/ARM/basic-arm-instructions.s b/llvm/test/MC/ARM/basic-arm-instructions.s
index 58993ded167..3708ec533f0 100644
--- a/llvm/test/MC/ARM/basic-arm-instructions.s
+++ b/llvm/test/MC/ARM/basic-arm-instructions.s
@@ -389,3 +389,62 @@ _func:
@ CHECK: clz r1, r2 @ encoding: [0x12,0x1f,0x6f,0xe1]
@ CHECK: clzeq r1, r2 @ encoding: [0x12,0x1f,0x6f,0x01]
+
+@------------------------------------------------------------------------------
+@ CMN
+@------------------------------------------------------------------------------
+ cmn r1, #0xf
+ cmn r1, r6
+ cmn r1, r6, lsl #10
+ cmn r1, r6, lsr #10
+ cmn sp, r6, lsr #10
+ cmn r1, r6, asr #10
+ cmn r1, r6, ror #10
+ cmn r7, r8, lsl r2
+ cmn sp, r8, lsr r2
+ cmn r7, r8, asr r2
+ cmn r7, r8, ror r2
+ cmn r1, r6, rrx
+
+@ CHECK: cmn r1, #15 @ encoding: [0x0f,0x00,0x71,0xe3]
+@ CHECK: cmn r1, r6 @ encoding: [0x06,0x00,0x71,0xe1]
+@ CHECK: cmn r1, r6, lsl #10 @ encoding: [0x06,0x05,0x71,0xe1]
+@ CHECK: cmn r1, r6, lsr #10 @ encoding: [0x26,0x05,0x71,0xe1]
+@ CHECK: cmn sp, r6, lsr #10 @ encoding: [0x26,0x05,0x7d,0xe1]
+@ CHECK: cmn r1, r6, asr #10 @ encoding: [0x46,0x05,0x71,0xe1]
+@ CHECK: cmn r1, r6, ror #10 @ encoding: [0x66,0x05,0x71,0xe1]
+@ CHECK: cmn r7, r8, lsl r2 @ encoding: [0x18,0x02,0x77,0xe1]
+@ CHECK: cmn sp, r8, lsr r2 @ encoding: [0x38,0x02,0x7d,0xe1]
+@ CHECK: cmn r7, r8, asr r2 @ encoding: [0x58,0x02,0x77,0xe1]
+@ CHECK: cmn r7, r8, ror r2 @ encoding: [0x78,0x02,0x77,0xe1]
+@ CHECK: cmn r1, r6, rrx @ encoding: [0x66,0x00,0x71,0xe1]
+
+@------------------------------------------------------------------------------
+@ CMP
+@------------------------------------------------------------------------------
+ cmp r1, #0xf
+ cmp r1, r6
+ cmp r1, r6, lsl #10
+ cmp r1, r6, lsr #10
+ cmp sp, r6, lsr #10
+ cmp r1, r6, asr #10
+ cmp r1, r6, ror #10
+ cmp r7, r8, lsl r2
+ cmp sp, r8, lsr r2
+ cmp r7, r8, asr r2
+ cmp r7, r8, ror r2
+ cmp r1, r6, rrx
+
+@ CHECK: cmp r1, #15 @ encoding: [0x0f,0x00,0x51,0xe3]
+@ CHECK: cmp r1, r6 @ encoding: [0x06,0x00,0x51,0xe1]
+@ CHECK: cmp r1, r6, lsl #10 @ encoding: [0x06,0x05,0x51,0xe1]
+@ CHECK: cmp r1, r6, lsr #10 @ encoding: [0x26,0x05,0x51,0xe1]
+@ CHECK: cmp sp, r6, lsr #10 @ encoding: [0x26,0x05,0x5d,0xe1]
+@ CHECK: cmp r1, r6, asr #10 @ encoding: [0x46,0x05,0x51,0xe1]
+@ CHECK: cmp r1, r6, ror #10 @ encoding: [0x66,0x05,0x51,0xe1]
+@ CHECK: cmp r7, r8, lsl r2 @ encoding: [0x18,0x02,0x57,0xe1]
+@ CHECK: cmp sp, r8, lsr r2 @ encoding: [0x38,0x02,0x5d,0xe1]
+@ CHECK: cmp r7, r8, asr r2 @ encoding: [0x58,0x02,0x57,0xe1]
+@ CHECK: cmp r7, r8, ror r2 @ encoding: [0x78,0x02,0x57,0xe1]
+@ CHECK: cmp r1, r6, rrx @ encoding: [0x66,0x00,0x51,0xe1]
+
OpenPOWER on IntegriCloud