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authorValery Pykhtin <Valery.Pykhtin@amd.com>2016-08-11 13:49:46 +0000
committerValery Pykhtin <Valery.Pykhtin@amd.com>2016-08-11 13:49:46 +0000
commit3048ff6ec392b6271ef32d88f020de111d21cbf1 (patch)
tree7e094c3288c64b3b2766a1a9d60dd58e544478d7
parentd6e1d7e521785f276421db93eb9359b7307c0658 (diff)
downloadbcm5719-llvm-3048ff6ec392b6271ef32d88f020de111d21cbf1.tar.gz
bcm5719-llvm-3048ff6ec392b6271ef32d88f020de111d21cbf1.zip
[AMDGPU] fix failure on printing of non-existing instruction operands.
Differential revision: https://reviews.llvm.org/D23323 llvm-svn: 278333
-rw-r--r--llvm/lib/Target/AMDGPU/InstPrinter/AMDGPUInstPrinter.cpp5
-rw-r--r--llvm/test/MC/Disassembler/AMDGPU/missing_op.txt5
2 files changed, 10 insertions, 0 deletions
diff --git a/llvm/lib/Target/AMDGPU/InstPrinter/AMDGPUInstPrinter.cpp b/llvm/lib/Target/AMDGPU/InstPrinter/AMDGPUInstPrinter.cpp
index 2932d3bb158..7dd0f009533 100644
--- a/llvm/lib/Target/AMDGPU/InstPrinter/AMDGPUInstPrinter.cpp
+++ b/llvm/lib/Target/AMDGPU/InstPrinter/AMDGPUInstPrinter.cpp
@@ -370,6 +370,11 @@ void AMDGPUInstPrinter::printImmediate64(uint64_t Imm, raw_ostream &O) {
void AMDGPUInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
raw_ostream &O) {
+ if (OpNo >= MI->getNumOperands()) {
+ O << "/*Missing OP" << OpNo << "*/";
+ return;
+ }
+
const MCOperand &Op = MI->getOperand(OpNo);
if (Op.isReg()) {
switch (Op.getReg()) {
diff --git a/llvm/test/MC/Disassembler/AMDGPU/missing_op.txt b/llvm/test/MC/Disassembler/AMDGPU/missing_op.txt
new file mode 100644
index 00000000000..a731f200cab
--- /dev/null
+++ b/llvm/test/MC/Disassembler/AMDGPU/missing_op.txt
@@ -0,0 +1,5 @@
+# RUN: llvm-mc -arch=amdgcn -mcpu=fiji -disassemble -show-encoding < %s | FileCheck %s -check-prefix=VI
+
+#TODO: this test will fail when we fix v_interp_p2_f32 signature, remove it then
+#VI: v_interp_p2_f32 16, [/*Missing OP1*/], /*Missing OP2*/, /*Missing OP3*/, /*Missing OP4*/
+0xd4 0x41 0x1d 0xd4
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