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| author | Daniel Dunbar <daniel@zuster.org> | 2009-08-28 08:08:22 +0000 |
|---|---|---|
| committer | Daniel Dunbar <daniel@zuster.org> | 2009-08-28 08:08:22 +0000 |
| commit | 3033db244825308762970786d841cc629df09339 (patch) | |
| tree | eeebe51fedfeae6fe8ae3a86da277200f42db7d7 | |
| parent | aa74a0c3b5a93777115ae07515a56020c78fabc7 (diff) | |
| download | bcm5719-llvm-3033db244825308762970786d841cc629df09339.tar.gz bcm5719-llvm-3033db244825308762970786d841cc629df09339.zip | |
Fix -Asserts warning, round two.
llvm-svn: 80354
| -rw-r--r-- | llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp | 5 |
1 files changed, 2 insertions, 3 deletions
diff --git a/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp b/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp index bc485daf6e9..1c41073077a 100644 --- a/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp +++ b/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp @@ -1057,12 +1057,11 @@ ARMBaseRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, if (Done) return; - const TargetInstrDesc &Desc = MI.getDesc(); - // If we get here, the immediate doesn't fit into the instruction. We folded // as much as possible above, handle the rest, providing a register that is // SP+LargeImm. - assert((Offset || (Desc.TSFlags & ARMII::AddrModeMask) == ARMII::AddrMode4) && + assert((Offset || + (MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrMode4) && "This code isn't needed if offset already handled!"); // Insert a set of r12 with the full address: r12 = sp + offset |
