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authorAndrea Di Biagio <Andrea_DiBiagio@sn.scee.net>2019-08-27 18:20:34 +0000
committerAndrea Di Biagio <Andrea_DiBiagio@sn.scee.net>2019-08-27 18:20:34 +0000
commit2f51a43f8c2b117e69a45eae6a7c849e035a793b (patch)
treeb0313ac4bae6ffe68f811c8d19b1bc52894aaf6d
parent2d247359cc399d283ae00c6b869ee05617f36e2b (diff)
downloadbcm5719-llvm-2f51a43f8c2b117e69a45eae6a7c849e035a793b.tar.gz
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[Tblgen][MCA] Add the ability to mark groups as LoadQueue and StoreQueue. NFCI
Before this patch, users were not allowed to optionally mark processor resource groups as load/store queues. That is because tablegen class MemoryQueue was originally declared as expecting a ProcResource template argument (instead of a more generic ProcResourceKind). That was an oversight, since the original intention from D54957 was to let user mark any processor resource as either load/store queue. This patch adds the ability to use processor resource groups in MemoryQueue definitions. This is not a user visible change. Differential Revision: https://reviews.llvm.org/D66810 llvm-svn: 370091
-rw-r--r--llvm/include/llvm/Target/TargetSchedule.td8
-rw-r--r--llvm/lib/MCA/HardwareUnits/LSUnit.cpp4
2 files changed, 6 insertions, 6 deletions
diff --git a/llvm/include/llvm/Target/TargetSchedule.td b/llvm/include/llvm/Target/TargetSchedule.td
index a36d259df83..24f37e94da9 100644
--- a/llvm/include/llvm/Target/TargetSchedule.td
+++ b/llvm/include/llvm/Target/TargetSchedule.td
@@ -563,10 +563,10 @@ class RetireControlUnit<int bufferSize, int retirePerCycle> {
// Base class for Load/StoreQueue. It is used to identify processor resources
// which describe load/store queues in the LS unit.
-class MemoryQueue<ProcResource PR> {
- ProcResource QueueDescriptor = PR;
+class MemoryQueue<ProcResourceKind PR> {
+ ProcResourceKind QueueDescriptor = PR;
SchedMachineModel SchedModel = ?;
}
-class LoadQueue<ProcResource LDQueue> : MemoryQueue<LDQueue>;
-class StoreQueue<ProcResource STQueue> : MemoryQueue<STQueue>;
+class LoadQueue<ProcResourceKind LDQueue> : MemoryQueue<LDQueue>;
+class StoreQueue<ProcResourceKind STQueue> : MemoryQueue<STQueue>;
diff --git a/llvm/lib/MCA/HardwareUnits/LSUnit.cpp b/llvm/lib/MCA/HardwareUnits/LSUnit.cpp
index ac1a6a36547..0465f53ed36 100644
--- a/llvm/lib/MCA/HardwareUnits/LSUnit.cpp
+++ b/llvm/lib/MCA/HardwareUnits/LSUnit.cpp
@@ -29,12 +29,12 @@ LSUnitBase::LSUnitBase(const MCSchedModel &SM, unsigned LQ, unsigned SQ,
const MCExtraProcessorInfo &EPI = SM.getExtraProcessorInfo();
if (!LQSize && EPI.LoadQueueID) {
const MCProcResourceDesc &LdQDesc = *SM.getProcResource(EPI.LoadQueueID);
- LQSize = LdQDesc.BufferSize;
+ LQSize = std::max(0, LdQDesc.BufferSize);
}
if (!SQSize && EPI.StoreQueueID) {
const MCProcResourceDesc &StQDesc = *SM.getProcResource(EPI.StoreQueueID);
- SQSize = StQDesc.BufferSize;
+ SQSize = std::max(0, StQDesc.BufferSize);
}
}
}
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