diff options
| author | Evan Cheng <evan.cheng@apple.com> | 2007-04-17 20:23:34 +0000 |
|---|---|---|
| committer | Evan Cheng <evan.cheng@apple.com> | 2007-04-17 20:23:34 +0000 |
| commit | 2f45bf31c521a89dd944adcf575ddb5059959f51 (patch) | |
| tree | 7e4b921e4c2dd98b4d021f782c3310ccbec23d61 | |
| parent | 8387cf1100079652df3e8efd8059e2a0345e7a66 (diff) | |
| download | bcm5719-llvm-2f45bf31c521a89dd944adcf575ddb5059959f51.tar.gz bcm5719-llvm-2f45bf31c521a89dd944adcf575ddb5059959f51.zip | |
Change getAllocatableSet() so it returns allocatable registers for a specific register class.
llvm-svn: 36215
| -rw-r--r-- | llvm/include/llvm/Target/MRegisterInfo.h | 6 | ||||
| -rw-r--r-- | llvm/lib/Target/MRegisterInfo.cpp | 11 |
2 files changed, 11 insertions, 6 deletions
diff --git a/llvm/include/llvm/Target/MRegisterInfo.h b/llvm/include/llvm/Target/MRegisterInfo.h index 23472f548dc..509485ab97d 100644 --- a/llvm/include/llvm/Target/MRegisterInfo.h +++ b/llvm/include/llvm/Target/MRegisterInfo.h @@ -241,8 +241,10 @@ public: } /// getAllocatableSet - Returns a bitset indexed by register number - /// indicating if a register is allocatable or not. - BitVector getAllocatableSet(MachineFunction &MF) const; + /// indicating if a register is allocatable or not. If a register class is + /// specified, returns the subset for the class. + BitVector getAllocatableSet(MachineFunction &MF, + const TargetRegisterClass *RC = NULL) const; const TargetRegisterDesc &operator[](unsigned RegNo) const { assert(RegNo < NumRegs && diff --git a/llvm/lib/Target/MRegisterInfo.cpp b/llvm/lib/Target/MRegisterInfo.cpp index 08039208fe8..ae9f20372fc 100644 --- a/llvm/lib/Target/MRegisterInfo.cpp +++ b/llvm/lib/Target/MRegisterInfo.cpp @@ -34,13 +34,16 @@ MRegisterInfo::MRegisterInfo(const TargetRegisterDesc *D, unsigned NR, MRegisterInfo::~MRegisterInfo() {} -BitVector MRegisterInfo::getAllocatableSet(MachineFunction &MF) const { +BitVector MRegisterInfo::getAllocatableSet(MachineFunction &MF, + const TargetRegisterClass *RC) const { BitVector Allocatable(NumRegs); for (MRegisterInfo::regclass_iterator I = regclass_begin(), E = regclass_end(); I != E; ++I) { - const TargetRegisterClass *RC = *I; - for (TargetRegisterClass::iterator I = RC->allocation_order_begin(MF), - E = RC->allocation_order_end(MF); I != E; ++I) + const TargetRegisterClass *TRC = *I; + if (RC && TRC != RC) + continue; + for (TargetRegisterClass::iterator I = TRC->allocation_order_begin(MF), + E = TRC->allocation_order_end(MF); I != E; ++I) Allocatable.set(*I); } return Allocatable; |

