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| author | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2012-12-20 22:53:55 +0000 |
|---|---|---|
| committer | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2012-12-20 22:53:55 +0000 |
| commit | 2ea203694dc84448b8a251d6fc9d84360641564e (patch) | |
| tree | 6bc337354d494930dc3a514cd6d31753c829d0f6 | |
| parent | 4255c96aed546aee941f50842c18c21179a58848 (diff) | |
| download | bcm5719-llvm-2ea203694dc84448b8a251d6fc9d84360641564e.tar.gz bcm5719-llvm-2ea203694dc84448b8a251d6fc9d84360641564e.zip | |
MachineInstrBuilderize ARM.
llvm-svn: 170795
| -rw-r--r-- | llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp index b2c8d487fbc..a12e333fdcc 100644 --- a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp +++ b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp @@ -464,8 +464,9 @@ PredicateInstruction(MachineInstr *MI, unsigned Opc = MI->getOpcode(); if (isUncondBranchOpcode(Opc)) { MI->setDesc(get(getMatchingCondBranchOpcode(Opc))); - MI->addOperand(MachineOperand::CreateImm(Pred[0].getImm())); - MI->addOperand(MachineOperand::CreateReg(Pred[1].getReg(), false)); + MachineInstrBuilder(*MI->getParent()->getParent(), MI) + .addImm(Pred[0].getImm()) + .addReg(Pred[1].getReg()); return true; } @@ -1717,7 +1718,7 @@ MachineInstr *ARMBaseInstrInfo::optimizeSelect(MachineInstr *MI, // same register as operand 0. MachineOperand FalseReg = MI->getOperand(Invert ? 2 : 1); FalseReg.setImplicit(); - NewMI->addOperand(FalseReg); + NewMI.addOperand(FalseReg); NewMI->tieOperands(0, NewMI->getNumOperands() - 1); // The caller will erase MI, but not DefMI. |
