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| author | Krzysztof Parzyszek <kparzysz@codeaurora.org> | 2015-07-14 20:11:28 +0000 |
|---|---|---|
| committer | Krzysztof Parzyszek <kparzysz@codeaurora.org> | 2015-07-14 20:11:28 +0000 |
| commit | 2e82883620196a42d57737a06ed4bb5ed5502de2 (patch) | |
| tree | 1382c0cbdd7cc5ace92be9b23242feaaaf7d2e8c | |
| parent | 9e6dea1df8eeb432b9f988e437202d1cd4897cfa (diff) | |
| download | bcm5719-llvm-2e82883620196a42d57737a06ed4bb5ed5502de2.tar.gz bcm5719-llvm-2e82883620196a42d57737a06ed4bb5ed5502de2.zip | |
Fix Windows build: replace __func__ with LLVM_FUNCTION_NAME
llvm-svn: 242192
| -rw-r--r-- | llvm/lib/Target/Hexagon/HexagonGenPredicate.cpp | 9 |
1 files changed, 5 insertions, 4 deletions
diff --git a/llvm/lib/Target/Hexagon/HexagonGenPredicate.cpp b/llvm/lib/Target/Hexagon/HexagonGenPredicate.cpp index 9e31c64192a..6a97cd4bd86 100644 --- a/llvm/lib/Target/Hexagon/HexagonGenPredicate.cpp +++ b/llvm/lib/Target/Hexagon/HexagonGenPredicate.cpp @@ -202,7 +202,8 @@ void HexagonGenPredicate::collectPredicateGPR(MachineFunction &MF) { void HexagonGenPredicate::processPredicateGPR(const Register &Reg) { - DEBUG(dbgs() << __func__ << ": " << PrintReg(Reg.R, TRI, Reg.S) << "\n"); + DEBUG(dbgs() << LLVM_FUNCTION_NAME << ": " + << PrintReg(Reg.R, TRI, Reg.S) << "\n"); typedef MachineRegisterInfo::use_iterator use_iterator; use_iterator I = MRI->use_begin(Reg.R), E = MRI->use_end(); if (I == E) { @@ -229,7 +230,7 @@ Register HexagonGenPredicate::getPredRegFor(const Register &Reg) { if (F != G2P.end()) return F->second; - DEBUG(dbgs() << __func__ << ": " << PrintRegister(Reg, *TRI)); + DEBUG(dbgs() << LLVM_FUNCTION_NAME << ": " << PrintRegister(Reg, *TRI)); MachineInstr *DefI = MRI->getVRegDef(Reg.R); assert(DefI); unsigned Opc = DefI->getOpcode(); @@ -345,7 +346,7 @@ bool HexagonGenPredicate::isScalarPred(Register PredReg) { bool HexagonGenPredicate::convertToPredForm(MachineInstr *MI) { - DEBUG(dbgs() << __func__ << ": " << MI << " " << *MI); + DEBUG(dbgs() << LLVM_FUNCTION_NAME << ": " << MI << " " << *MI); unsigned Opc = MI->getOpcode(); assert(isConvertibleToPredForm(MI)); @@ -431,7 +432,7 @@ bool HexagonGenPredicate::convertToPredForm(MachineInstr *MI) { bool HexagonGenPredicate::eliminatePredCopies(MachineFunction &MF) { - DEBUG(dbgs() << __func__ << "\n"); + DEBUG(dbgs() << LLVM_FUNCTION_NAME << "\n"); const TargetRegisterClass *PredRC = &Hexagon::PredRegsRegClass; bool Changed = false; VectOfInst Erase; |
