[GlobalISel] Add a generic machine opcode for ADD.

The selection process being split into separate passes, we need generic opcodes
to translate the LLVM IR to target independent code.

This patch adds an opcode for addition: G_ADD.

Differential Revision: http://reviews.llvm.org/D15472

llvm-svn: 258333

6 files changed, 41 insertions, 7 deletions

diff --git a/llvm/include/llvm/Target/Target.td b/llvm/include/llvm/Target/Target.td
index c869341c384..2e8897df8e6 100644
--- a/llvm/include/llvm/Target/Target.td
+++ b/llvm/include/llvm/Target/Target.td
@@ -913,6 +913,17 @@ def FAULTING_LOAD_OP : Instruction {
   let usesCustomInserter = 1;
   let mayLoad = 1;
 }
+
+// Generic opcode used by the IRTranslator.
+// After ISel, this opcode should not appear.
+def G_ADD : Instruction {
+  let OutOperandList = (outs unknown:$dst);
+  let InOperandList = (ins unknown:$src1, unknown:$src2);
+  let AsmString = "";
+  let hasSideEffects = 0;
+  let isCommutable = 1;
+}
+// TODO: Add the other generic opcodes.
 }
 
 //===----------------------------------------------------------------------===//
diff --git a/llvm/include/llvm/Target/TargetOpcodes.h b/llvm/include/llvm/Target/TargetOpcodes.h
index db37bdb6258..e8c997d060b 100644
--- a/llvm/include/llvm/Target/TargetOpcodes.h
+++ b/llvm/include/llvm/Target/TargetOpcodes.h
@@ -129,9 +129,27 @@ enum {
   /// comparisons into existing memory operations.
   FAULTING_LOAD_OP = 22,
 
+  /// The following generic opcodes are not supposed to appear after ISel.
+  /// This is something we might want to relax, but for now, this is convenient
+  /// to produce diagnostic.
+  PRE_ISEL_GENERIC_OPCODE_START,
+  // Generic opcodes used before ISel are here.
+
+  /// Generic ADD instruction. This is an integer add.
+  G_ADD = PRE_ISEL_GENERIC_OPCODE_START,
+  // TODO: Add more generic opcodes as we move along.
+  // FIXME: Right now, we have to manually add any new opcode in
+  // CodeGenTarget.cpp for TableGen to pick them up.
+  // Moreover the order must match.
+
+  /// Marker for the end of the generic opcode.
+  /// This is used to check if an opcode is in the range of the
+  /// generic opcodes.
+  PRE_ISEL_GENERIC_OPCODE_END,
+
   /// BUILTIN_OP_END - This must be the last enum value in this list.
   /// The target-specific post-isel opcode values start here.
-  GENERIC_OP_END = FAULTING_LOAD_OP,
+  GENERIC_OP_END = PRE_ISEL_GENERIC_OPCODE_END,
 };
 } // end namespace TargetOpcode
 } // end namespace llvm
diff --git a/llvm/test/TableGen/trydecode-emission.td b/llvm/test/TableGen/trydecode-emission.td
index 91c0e123857..57e1bdd1fb0 100644
--- a/llvm/test/TableGen/trydecode-emission.td
+++ b/llvm/test/TableGen/trydecode-emission.td
@@ -36,8 +36,8 @@ def InstB : TestInstruction {
 // CHECK:      /* 0 */       MCD::OPC_ExtractField, 4, 4,  // Inst{7-4} ...
 // CHECK-NEXT: /* 3 */       MCD::OPC_FilterValue, 0, 14, 0, // Skip to: 21
 // CHECK-NEXT: /* 7 */       MCD::OPC_CheckField, 2, 2, 0, 5, 0, // Skip to: 18
-// CHECK-NEXT: /* 13 */      MCD::OPC_TryDecode, 24, 0, 0, 0, // Opcode: InstB, skip to: 18
-// CHECK-NEXT: /* 18 */      MCD::OPC_Decode, 23, 1, // Opcode: InstA
+// CHECK-NEXT: /* 13 */      MCD::OPC_TryDecode, 25, 0, 0, 0, // Opcode: InstB, skip to: 18
+// CHECK-NEXT: /* 18 */      MCD::OPC_Decode, 24, 1, // Opcode: InstA
 // CHECK-NEXT: /* 21 */      MCD::OPC_Fail,
 
 // CHECK: if (DecodeInstB(MI, insn, Address, Decoder) == MCDisassembler::Fail) { DecodeComplete = false; return MCDisassembler::Fail; }
diff --git a/llvm/test/TableGen/trydecode-emission2.td b/llvm/test/TableGen/trydecode-emission2.td
index 56ca6d33c24..f4b0dfade1b 100644
--- a/llvm/test/TableGen/trydecode-emission2.td
+++ b/llvm/test/TableGen/trydecode-emission2.td
@@ -35,9 +35,9 @@ def InstB : TestInstruction {
 // CHECK-NEXT: /* 7 */       MCD::OPC_ExtractField, 5, 3,  // Inst{7-5} ...
 // CHECK-NEXT: /* 10 */      MCD::OPC_FilterValue, 0, 22, 0, // Skip to: 36
 // CHECK-NEXT: /* 14 */      MCD::OPC_CheckField, 0, 2, 3, 5, 0, // Skip to: 25
-// CHECK-NEXT: /* 20 */      MCD::OPC_TryDecode, 24, 0, 0, 0, // Opcode: InstB, skip to: 25
+// CHECK-NEXT: /* 20 */      MCD::OPC_TryDecode, 25, 0, 0, 0, // Opcode: InstB, skip to: 25
 // CHECK-NEXT: /* 25 */      MCD::OPC_CheckField, 3, 2, 0, 5, 0, // Skip to: 36
-// CHECK-NEXT: /* 31 */      MCD::OPC_TryDecode, 23, 1, 0, 0, // Opcode: InstA, skip to: 36
+// CHECK-NEXT: /* 31 */      MCD::OPC_TryDecode, 24, 1, 0, 0, // Opcode: InstA, skip to: 36
 // CHECK-NEXT: /* 36 */      MCD::OPC_Fail,
 
 // CHECK: if (DecodeInstB(MI, insn, Address, Decoder) == MCDisassembler::Fail) { DecodeComplete = false; return MCDisassembler::Fail; }
diff --git a/llvm/test/TableGen/trydecode-emission3.td b/llvm/test/TableGen/trydecode-emission3.td
index ad21eefa897..2ccf2f49ff9 100644
--- a/llvm/test/TableGen/trydecode-emission3.td
+++ b/llvm/test/TableGen/trydecode-emission3.td
@@ -37,8 +37,8 @@ def InstB : TestInstruction {
 // CHECK:      /* 0 */       MCD::OPC_ExtractField, 4, 4,  // Inst{7-4} ...
 // CHECK-NEXT: /* 3 */       MCD::OPC_FilterValue, 0, 14, 0, // Skip to: 21
 // CHECK-NEXT: /* 7 */       MCD::OPC_CheckField, 2, 2, 0, 5, 0, // Skip to: 18
-// CHECK-NEXT: /* 13 */      MCD::OPC_TryDecode, 24, 0, 0, 0, // Opcode: InstB, skip to: 18
-// CHECK-NEXT: /* 18 */      MCD::OPC_Decode, 23, 1, // Opcode: InstA
+// CHECK-NEXT: /* 13 */      MCD::OPC_TryDecode, 25, 0, 0, 0, // Opcode: InstB, skip to: 18
+// CHECK-NEXT: /* 18 */      MCD::OPC_Decode, 24, 1, // Opcode: InstA
 // CHECK-NEXT: /* 21 */      MCD::OPC_Fail,
 
 // CHECK: if (DecodeInstBOp(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { DecodeComplete = false; return MCDisassembler::Fail; }
diff --git a/llvm/utils/TableGen/CodeGenTarget.cpp b/llvm/utils/TableGen/CodeGenTarget.cpp
index 3cae27f82b0..a22418c6eae 100644
--- a/llvm/utils/TableGen/CodeGenTarget.cpp
+++ b/llvm/utils/TableGen/CodeGenTarget.cpp
@@ -301,6 +301,9 @@ GetInstByName(const char *Name,
 /// their enum value.
 void CodeGenTarget::ComputeInstrsByEnum() const {
   // The ordering here must match the ordering in TargetOpcodes.h.
+  // FIXME: It would be nice to have the opcode directly extracted
+  // to avoid potential errors. At the very, least a compile time
+  // error would be appreciated if the order does not match.
   static const char *const FixedInstrs[] = {
       "PHI",          "INLINEASM",     "CFI_INSTRUCTION",  "EH_LABEL",
       "GC_LABEL",     "KILL",          "EXTRACT_SUBREG",   "INSERT_SUBREG",
@@ -308,6 +311,8 @@ void CodeGenTarget::ComputeInstrsByEnum() const {
       "REG_SEQUENCE", "COPY",          "BUNDLE",           "LIFETIME_START",
       "LIFETIME_END", "STACKMAP",      "PATCHPOINT",       "LOAD_STACK_GUARD",
       "STATEPOINT",   "LOCAL_ESCAPE",   "FAULTING_LOAD_OP",
+      // Generic opcodes for GlobalISel start here.
+      "G_ADD",
       nullptr};
   const auto &Insts = getInstructions();
   for (const char *const *p = FixedInstrs; *p; ++p) {