diff options
| author | Simon Pilgrim <llvm-dev@redking.me.uk> | 2016-05-15 20:22:50 +0000 |
|---|---|---|
| committer | Simon Pilgrim <llvm-dev@redking.me.uk> | 2016-05-15 20:22:50 +0000 |
| commit | 2d4bf1042b6431c9f36e6050b23d0734fee34607 (patch) | |
| tree | 62acc753916230e6f70e71e7c7879b3447b4dea7 | |
| parent | fbe97bc15aa0fec2facacd24ca27a9abd2a72859 (diff) | |
| download | bcm5719-llvm-2d4bf1042b6431c9f36e6050b23d0734fee34607.tar.gz bcm5719-llvm-2d4bf1042b6431c9f36e6050b23d0734fee34607.zip | |
[X86][SSE] Simplify zero'th index extract element matching
llvm-svn: 269615
| -rw-r--r-- | llvm/lib/Target/X86/X86ISelLowering.cpp | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index 60b42c63bb5..d8c60b55e66 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -12235,10 +12235,11 @@ X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op, MVT VT = Op.getSimpleValueType(); // TODO: handle v16i8. if (VT.getSizeInBits() == 16) { - if (isNullConstant(Idx)) + if (IdxVal == 0) return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32, DAG.getBitcast(MVT::v4i32, Vec), Idx)); + // Transform it so it match pextrw which produces a 32-bit result. MVT EltVT = MVT::i32; SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT, Vec, Idx); @@ -12262,7 +12263,7 @@ X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op, // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught // to match extract_elt for f64. - if (isNullConstant(Idx)) + if (IdxVal == 0) return Op; // UNPCKHPD the element to the lowest double word, then movsd. |
