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| author | Sanjay Patel <spatel@rotateright.com> | 2016-10-17 15:58:28 +0000 |
|---|---|---|
| committer | Sanjay Patel <spatel@rotateright.com> | 2016-10-17 15:58:28 +0000 |
| commit | 2cf6bfaf7383bb6bff0ea288a1020516e1abd868 (patch) | |
| tree | 5fe83644026ae550eaca9e618c918a39190e15a2 | |
| parent | 95db75791e48852e5cfdf02236971453f43ff389 (diff) | |
| download | bcm5719-llvm-2cf6bfaf7383bb6bff0ea288a1020516e1abd868.tar.gz bcm5719-llvm-2cf6bfaf7383bb6bff0ea288a1020516e1abd868.zip | |
[DAG] optimize away an arithmetic-right-shift of a 0 or -1 value
This came up as part of:
https://reviews.llvm.org/D25485
Note that the vector case is missed because ComputeNumSignBits() is deficient for vectors.
llvm-svn: 284395
| -rw-r--r-- | llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 4 | ||||
| -rw-r--r-- | llvm/test/CodeGen/X86/sar_fold64.ll | 3 |
2 files changed, 4 insertions, 3 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp index 44a49e848aa..f460d529d05 100644 --- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp @@ -4740,6 +4740,10 @@ SDValue DAGCombiner::visitSRA(SDNode *N) { EVT VT = N0.getValueType(); unsigned OpSizeInBits = VT.getScalarSizeInBits(); + // Arithmetic shifting an all-sign-bit value is a no-op. + if (DAG.ComputeNumSignBits(N0) == OpSizeInBits) + return N0; + // fold vector ops ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); if (VT.isVector()) { diff --git a/llvm/test/CodeGen/X86/sar_fold64.ll b/llvm/test/CodeGen/X86/sar_fold64.ll index b8bd04dbb22..80c632b1f6a 100644 --- a/llvm/test/CodeGen/X86/sar_fold64.ll +++ b/llvm/test/CodeGen/X86/sar_fold64.ll @@ -57,14 +57,11 @@ define i32 @shl56sar57(i64 %a) #0 { ret i32 %3 } -; FIXME - define i8 @all_sign_bit_ashr(i8 %x) { ; CHECK-LABEL: all_sign_bit_ashr: ; CHECK: # BB#0: ; CHECK-NEXT: andb $1, %dil ; CHECK-NEXT: negb %dil -; CHECK-NEXT: sarb $6, %dil ; CHECK-NEXT: movl %edi, %eax ; CHECK-NEXT: retq ; |
