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authorJuergen Ributzka <juergen@apple.com>2014-08-13 21:39:18 +0000
committerJuergen Ributzka <juergen@apple.com>2014-08-13 21:39:18 +0000
commit2cbcf7aad91bccd7123c0be16fc18273f7e2e82d (patch)
treeebf37ebff5a39e6984baf749724d1db335abc552
parent5ae43a136bf9483b1a77bb212da8d7b8e80ef979 (diff)
downloadbcm5719-llvm-2cbcf7aad91bccd7123c0be16fc18273f7e2e82d.tar.gz
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[FastISel][ARM] Fix a bug in the integer materialization code.
getRegClassFor returns the incorrect register class when in Thumb2 mode. This fix simply manually selects the register class as in the code just a few lines above. There is no test case for this code, because the code is currently unreachable. This will be changed in a future commit and existing test cases will exercise this code. llvm-svn: 215583
-rw-r--r--llvm/lib/Target/ARM/ARMFastISel.cpp4
1 files changed, 3 insertions, 1 deletions
diff --git a/llvm/lib/Target/ARM/ARMFastISel.cpp b/llvm/lib/Target/ARM/ARMFastISel.cpp
index aff2fd9ba4d..5d33303ffa1 100644
--- a/llvm/lib/Target/ARM/ARMFastISel.cpp
+++ b/llvm/lib/Target/ARM/ARMFastISel.cpp
@@ -536,7 +536,9 @@ unsigned ARMFastISel::ARMMaterializeInt(const Constant *C, MVT VT) {
(ARM_AM::getSOImmVal(Imm) != -1);
if (UseImm) {
unsigned Opc = isThumb2 ? ARM::t2MVNi : ARM::MVNi;
- unsigned ImmReg = createResultReg(TLI.getRegClassFor(MVT::i32));
+ const TargetRegisterClass *RC = isThumb2 ? &ARM::rGPRRegClass :
+ &ARM::GPRRegClass;
+ unsigned ImmReg = createResultReg(RC);
AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
TII.get(Opc), ImmReg)
.addImm(Imm));
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