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| author | Anton Korobeynikov <asl@math.spbu.ru> | 2010-04-07 18:20:07 +0000 |
|---|---|---|
| committer | Anton Korobeynikov <asl@math.spbu.ru> | 2010-04-07 18:20:07 +0000 |
| commit | 2cba05bbe134768b876fbfa72adfe44a4414e95c (patch) | |
| tree | 370d0a8cfedc6d7354109793d37b8fb43e81db32 | |
| parent | 2063705d918b08802d29e6c1dc3b89e73fbfed9f (diff) | |
| download | bcm5719-llvm-2cba05bbe134768b876fbfa72adfe44a4414e95c.tar.gz bcm5719-llvm-2cba05bbe134768b876fbfa72adfe44a4414e95c.zip | |
Some easy NEON scheduling goodness for A9
llvm-svn: 100651
| -rw-r--r-- | llvm/lib/Target/ARM/ARMScheduleV7.td | 54 |
1 files changed, 53 insertions, 1 deletions
diff --git a/llvm/lib/Target/ARM/ARMScheduleV7.td b/llvm/lib/Target/ARM/ARMScheduleV7.td index 77142ce5cdc..539732010a0 100644 --- a/llvm/lib/Target/ARM/ARMScheduleV7.td +++ b/llvm/lib/Target/ARM/ARMScheduleV7.td @@ -780,7 +780,59 @@ def CortexA9Itineraries : ProcessorItineraries<[ InstrItinData<IIC_fpMOVDI, [InstrStage2<1, [FU_DRegsVFP], 0, Required>, InstrStage2<2, [FU_DRegsN], 0, Reserved>, InstrStage<1, [FU_Pipe0, FU_Pipe1]>, - InstrStage<1, [FU_NPipe]>], [1, 1, 1]> + InstrStage<1, [FU_NPipe]>], [1, 1, 1]>, + // NEON + // Issue through integer pipeline, and execute in NEON unit. + + // + // Double-register Integer Binary + InstrItinData<IIC_VBINiD, [InstrStage2<1, [FU_DRegsN], 0, Required>, + // Extra 3 latency cycle since wbck is 6 cycles + InstrStage2<7, [FU_DRegsVFP], 0, Reserved>, + InstrStage<1, [FU_Pipe0, FU_Pipe1]>, + InstrStage<1, [FU_NPipe]>], [3, 2, 2]>, + // + // Quad-register Integer Binary + InstrItinData<IIC_VBINiQ, [InstrStage2<1, [FU_DRegsN], 0, Required>, + // Extra 3 latency cycle since wbck is 6 cycles + InstrStage2<7, [FU_DRegsVFP], 0, Reserved>, + InstrStage<1, [FU_Pipe0, FU_Pipe1]>, + InstrStage<1, [FU_NPipe]>], [3, 2, 2]>, + // + // Double-register Integer Subtract + InstrItinData<IIC_VSUBiD, [InstrStage2<1, [FU_DRegsN], 0, Required>, + // Extra 3 latency cycle since wbck is 6 cycles + InstrStage2<7, [FU_DRegsVFP], 0, Reserved>, + InstrStage<1, [FU_Pipe0, FU_Pipe1]>, + InstrStage<1, [FU_NPipe]>], [3, 2, 1]>, + // + // Quad-register Integer Subtract + InstrItinData<IIC_VSUBiQ, [InstrStage2<1, [FU_DRegsN], 0, Required>, + // Extra 3 latency cycle since wbck is 6 cycles + InstrStage2<7, [FU_DRegsVFP], 0, Reserved>, + InstrStage<1, [FU_Pipe0, FU_Pipe1]>, + InstrStage<1, [FU_NPipe]>], [3, 2, 1]>, + // + // Double-register Integer Shift + InstrItinData<IIC_VSHLiD, [InstrStage2<1, [FU_DRegsN], 0, Required>, + // Extra 3 latency cycle since wbck is 6 cycles + InstrStage2<7, [FU_DRegsVFP], 0, Reserved>, + InstrStage<1, [FU_Pipe0, FU_Pipe1]>, + InstrStage<1, [FU_NPipe]>], [3, 1, 1]>, + // + // Double-register Integer Binary (4 cycle) + InstrItinData<IIC_VBINi4D, [InstrStage2<1, [FU_DRegsN], 0, Required>, + // Extra 3 latency cycle since wbck is 6 cycles + InstrStage2<7, [FU_DRegsVFP], 0, Reserved>, + InstrStage<1, [FU_Pipe0, FU_Pipe1]>, + InstrStage<1, [FU_NPipe]>], [4, 2, 2]>, + // + // Quad-register Integer Binary (4 cycle) + InstrItinData<IIC_VBINi4Q, [InstrStage2<1, [FU_DRegsN], 0, Required>, + // Extra 3 latency cycle since wbck is 6 cycles + InstrStage2<7, [FU_DRegsVFP], 0, Reserved>, + InstrStage<1, [FU_Pipe0, FU_Pipe1]>, + InstrStage<1, [FU_NPipe]>], [4, 2, 2]> ]>; |
