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| author | Matthias Braun <matze@braunis.de> | 2016-03-28 18:18:41 +0000 |
|---|---|---|
| committer | Matthias Braun <matze@braunis.de> | 2016-03-28 18:18:41 +0000 |
| commit | 2bd8eeb6b7ab8b39a884f37cd24e7373f5f0ea35 (patch) | |
| tree | 9578d46243de3335036e9d225b7d3130172cefac | |
| parent | 6a6bc750d5ba2a37438607e360346443268fe8bc (diff) | |
| download | bcm5719-llvm-2bd8eeb6b7ab8b39a884f37cd24e7373f5f0ea35.tar.gz bcm5719-llvm-2bd8eeb6b7ab8b39a884f37cd24e7373f5f0ea35.zip | |
CodeGen: Correct specification of PHI nodes
They do have a def machine operand.
Fixing the definition is necessary for an upcoming patch.
Differential Revision: http://reviews.llvm.org/D18384
llvm-svn: 264607
| -rw-r--r-- | llvm/include/llvm/Target/Target.td | 2 | ||||
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/valu-i1.ll | 4 |
2 files changed, 3 insertions, 3 deletions
diff --git a/llvm/include/llvm/Target/Target.td b/llvm/include/llvm/Target/Target.td index 654a008f660..7c55442f479 100644 --- a/llvm/include/llvm/Target/Target.td +++ b/llvm/include/llvm/Target/Target.td @@ -773,7 +773,7 @@ class InstrInfo { let isCodeGenOnly = 1, isPseudo = 1, hasNoSchedulingInfo = 1, Namespace = "TargetOpcode" in { def PHI : Instruction { - let OutOperandList = (outs); + let OutOperandList = (outs unknown:$dst); let InOperandList = (ins variable_ops); let AsmString = "PHINODE"; } diff --git a/llvm/test/CodeGen/AMDGPU/valu-i1.ll b/llvm/test/CodeGen/AMDGPU/valu-i1.ll index 4c79dc482b6..ffa0110a14b 100644 --- a/llvm/test/CodeGen/AMDGPU/valu-i1.ll +++ b/llvm/test/CodeGen/AMDGPU/valu-i1.ll @@ -138,11 +138,11 @@ exit: ; SI: BB#4: ; SI: buffer_store_dword ; SI: v_cmp_ge_i64_e64 [[CMP:s\[[0-9]+:[0-9]+\]]] -; SI: s_or_b64 [[COND_STATE]], [[CMP]], [[COND_STATE]] +; SI: s_or_b64 [[TMP:s\[[0-9]+:[0-9]+\]]], [[CMP]], [[COND_STATE]] ; SI: BB3_5: ; SI: s_or_b64 exec, exec, [[ORNEG2]] -; SI: s_or_b64 [[COND_STATE]], [[ORNEG2]], [[COND_STATE]] +; SI: s_or_b64 [[COND_STATE]], [[ORNEG2]], [[TMP]] ; SI: s_andn2_b64 exec, exec, [[COND_STATE]] ; SI: s_cbranch_execnz BB3_3 |
