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authorJim Grosbach <grosbach@apple.com>2010-05-07 18:34:55 +0000
committerJim Grosbach <grosbach@apple.com>2010-05-07 18:34:55 +0000
commit2a41cad900b99eaf0ae50af831259ab3c1f752f5 (patch)
tree85c04dc7a2840cf00ab3fe6c4c1fbc6618bfef3e
parent4423abd73496b38cd78915542145353ae86c0001 (diff)
downloadbcm5719-llvm-2a41cad900b99eaf0ae50af831259ab3c1f752f5.tar.gz
bcm5719-llvm-2a41cad900b99eaf0ae50af831259ab3c1f752f5.zip
Clean up the conditional for handling of sign_extend_inreg based on
whether the extract instructions are available. rdar://7956878 llvm-svn: 103277
-rw-r--r--llvm/lib/Target/ARM/ARMISelLowering.cpp7
-rw-r--r--llvm/test/CodeGen/Thumb2/sign_extend_inreg.ll22
2 files changed, 27 insertions, 2 deletions
diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp
index f8c17b8ac2d..d8582ecf05f 100644
--- a/llvm/lib/Target/ARM/ARMISelLowering.cpp
+++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp
@@ -393,8 +393,11 @@ ARMTargetLowering::ARMTargetLowering(TargetMachine &TM)
setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
setOperationAction(ISD::MEMBARRIER, MVT::Other, Custom);
- if (!Subtarget->hasV6Ops() && (!Subtarget->isThumb2()
- || !Subtarget->hasT2ExtractPack())) {
+ // If the subtarget does not have extract instructions, sign_extend_inreg
+ // needs to be expanded. Extract is available in ARM mode on v6 and up,
+ // and on most Thumb2 implementations.
+ if ((!Subtarget->isThumb() && !Subtarget->hasV6Ops())
+ || (Subtarget->isThumb2() && !Subtarget->hasT2ExtractPack())) {
setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand);
}
diff --git a/llvm/test/CodeGen/Thumb2/sign_extend_inreg.ll b/llvm/test/CodeGen/Thumb2/sign_extend_inreg.ll
new file mode 100644
index 00000000000..9a02c1caeb6
--- /dev/null
+++ b/llvm/test/CodeGen/Thumb2/sign_extend_inreg.ll
@@ -0,0 +1,22 @@
+; RUN: llc < %s -mcpu=cortex-a8 | FileCheck %s -check-prefix=CHECK-A8
+; RUN: llc < %s -mcpu=cortex-m3 | FileCheck %s -check-prefix=CHECK-M3
+
+target triple = "thumbv7-apple-darwin10"
+
+define arm_apcscc i32 @f1(i16* %ptr) nounwind {
+; CHECK-A8: f1
+; CHECK-A8: sxth
+; CHECK-M3: f1
+; CHECK-M3-NOT: sxth
+; CHECK-M3: bx lr
+ %1 = load i16* %ptr
+ %2 = icmp eq i16 %1, 1
+ %3 = sext i16 %1 to i32
+ br i1 %2, label %.next, label %.exit
+
+.next:
+ br label %.exit
+
+.exit:
+ ret i32 %3
+}
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