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| author | Amara Emerson <aemerson@apple.com> | 2019-08-13 23:51:20 +0000 |
|---|---|---|
| committer | Amara Emerson <aemerson@apple.com> | 2019-08-13 23:51:20 +0000 |
| commit | 2a312fc9899ba66c519401b9c98b0880e405c855 (patch) | |
| tree | 9eb981441abf81ef3195ad68080c9d11b110dd5e | |
| parent | 216944ee035aa720cc94034f3aa68064eda80469 (diff) | |
| download | bcm5719-llvm-2a312fc9899ba66c519401b9c98b0880e405c855.tar.gz bcm5719-llvm-2a312fc9899ba66c519401b9c98b0880e405c855.zip | |
[AArch64][GlobalISel] RBS: Treat s128s like vectors when unmerging.
The destinations should be FPRs (for now).
Differential Revision: https://reviews.llvm.org/D66184
llvm-svn: 368775
| -rw-r--r-- | llvm/lib/Target/AArch64/AArch64RegisterBankInfo.cpp | 2 | ||||
| -rw-r--r-- | llvm/test/CodeGen/AArch64/GlobalISel/regbankselect-unmerge-vec.mir | 24 |
2 files changed, 25 insertions, 1 deletions
diff --git a/llvm/lib/Target/AArch64/AArch64RegisterBankInfo.cpp b/llvm/lib/Target/AArch64/AArch64RegisterBankInfo.cpp index 63cdf326ac3..8ec73aa3c04 100644 --- a/llvm/lib/Target/AArch64/AArch64RegisterBankInfo.cpp +++ b/llvm/lib/Target/AArch64/AArch64RegisterBankInfo.cpp @@ -768,7 +768,7 @@ AArch64RegisterBankInfo::getInstrMapping(const MachineInstr &MI) const { LLT SrcTy = MRI.getType(MI.getOperand(MI.getNumOperands()-1).getReg()); // UNMERGE into scalars from a vector should always use FPR. // Likewise if any of the uses are FP instructions. - if (SrcTy.isVector() || + if (SrcTy.isVector() || SrcTy == LLT::scalar(128) || any_of(MRI.use_instructions(MI.getOperand(0).getReg()), [&](MachineInstr &MI) { return onlyUsesFP(MI, MRI, TRI); })) { // Set the register bank of every operand to FPR. diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/regbankselect-unmerge-vec.mir b/llvm/test/CodeGen/AArch64/GlobalISel/regbankselect-unmerge-vec.mir index 3123de27c1e..d1032548090 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/regbankselect-unmerge-vec.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/regbankselect-unmerge-vec.mir @@ -24,3 +24,27 @@ body: | RET_ReallyLR implicit $x0 ... +--- +name: unmerge_s128 +alignment: 2 +legalized: true +tracksRegLiveness: true +frameInfo: + maxCallFrameSize: 0 +body: | + bb.0: + liveins: $q0 + + ; s128 should be treated as an FPR/vector because it can't live on GPR bank. + ; CHECK-LABEL: name: unmerge_s128 + ; CHECK: liveins: $q0 + ; CHECK: [[COPY:%[0-9]+]]:fpr(s128) = COPY $q0 + ; CHECK: [[UV:%[0-9]+]]:fpr(s64), [[UV1:%[0-9]+]]:fpr(s64) = G_UNMERGE_VALUES [[COPY]](s128) + ; CHECK: $x0 = COPY [[UV]](s64) + ; CHECK: RET_ReallyLR implicit $x0 + %0:_(s128) = COPY $q0 + %1:_(s64), %2:_(s64) = G_UNMERGE_VALUES %0(s128) + $x0 = COPY %1(s64) + RET_ReallyLR implicit $x0 + +... |
