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| author | Aditya Nandakumar <aditya_nandakumar@apple.com> | 2018-08-20 18:43:19 +0000 | 
|---|---|---|
| committer | Aditya Nandakumar <aditya_nandakumar@apple.com> | 2018-08-20 18:43:19 +0000 | 
| commit | 2a08285cf370d1057fbda824100a846621ac1a47 (patch) | |
| tree | f2630342bce3bc25141a2120ac3f1abca8dc3e9f | |
| parent | 6ac905926f8cf5ef940c6c3f631dbe49be9911c5 (diff) | |
| download | bcm5719-llvm-2a08285cf370d1057fbda824100a846621ac1a47.tar.gz bcm5719-llvm-2a08285cf370d1057fbda824100a846621ac1a47.zip  | |
Revert "Revert r339977: [GISel]: Add Opcodes for a few LLVM Intrinsics"
This reverts commit 7debc334e6421bb5251ef8f18e97166dfc7dd787.
I missed updating legalizer-info-validation.mir as I had assertions
turned off in my build and that specific test requires asserts. Fixed it
now.
llvm-svn: 340197
5 files changed, 57 insertions, 0 deletions
diff --git a/llvm/include/llvm/Support/TargetOpcodes.def b/llvm/include/llvm/Support/TargetOpcodes.def index 9143e5b9dd9..dfd15ac22d9 100644 --- a/llvm/include/llvm/Support/TargetOpcodes.def +++ b/llvm/include/llvm/Support/TargetOpcodes.def @@ -268,6 +268,12 @@ HANDLE_TARGET_OPCODE(G_INTTOPTR)  /// COPY is the relevant instruction.  HANDLE_TARGET_OPCODE(G_BITCAST) +/// INTRINSIC trunc intrinsic. +HANDLE_TARGET_OPCODE(G_INTRINSIC_TRUNC) + +/// INTRINSIC round intrinsic. +HANDLE_TARGET_OPCODE(G_INTRINSIC_ROUND) +  /// Generic load (including anyext load)  HANDLE_TARGET_OPCODE(G_LOAD) diff --git a/llvm/include/llvm/Target/GenericOpcodes.td b/llvm/include/llvm/Target/GenericOpcodes.td index 90c121dfe3a..2a2bef2fb38 100644 --- a/llvm/include/llvm/Target/GenericOpcodes.td +++ b/llvm/include/llvm/Target/GenericOpcodes.td @@ -513,6 +513,21 @@ def G_FLOG2 : GenericInstruction {  }  //------------------------------------------------------------------------------ +// Opcodes for LLVM Intrinsics +//------------------------------------------------------------------------------ +def G_INTRINSIC_TRUNC : GenericInstruction { +  let OutOperandList = (outs type0:$dst); +  let InOperandList = (ins type0:$src1); +  let hasSideEffects = 0; +} + +def G_INTRINSIC_ROUND : GenericInstruction { +  let OutOperandList = (outs type0:$dst); +  let InOperandList = (ins type0:$src1); +  let hasSideEffects = 0; +} + +//------------------------------------------------------------------------------  // Memory ops  //------------------------------------------------------------------------------ diff --git a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp index 81bebdfd237..c58b2ef0f28 100644 --- a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp +++ b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp @@ -861,6 +861,16 @@ bool IRTranslator::translateKnownIntrinsic(const CallInst &CI, Intrinsic::ID ID,          .addDef(getOrCreateVReg(CI))          .addUse(getOrCreateVReg(*CI.getArgOperand(0)));      return true; +  case Intrinsic::trunc: +    MIRBuilder.buildInstr(TargetOpcode::G_INTRINSIC_TRUNC) +        .addDef(getOrCreateVReg(CI)) +        .addUse(getOrCreateVReg(*CI.getArgOperand(0))); +    return true; +  case Intrinsic::round: +    MIRBuilder.buildInstr(TargetOpcode::G_INTRINSIC_ROUND) +        .addDef(getOrCreateVReg(CI)) +        .addUse(getOrCreateVReg(*CI.getArgOperand(0))); +    return true;    case Intrinsic::fma:      MIRBuilder.buildInstr(TargetOpcode::G_FMA)          .addDef(getOrCreateVReg(CI)) diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll index 75615e9d6c1..cf30558d5d6 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll +++ b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll @@ -1408,6 +1408,26 @@ define float @test_fabs_intrin(float %a) {    ret float %res  } +declare float @llvm.trunc.f32(float) +define float @test_intrinsic_trunc(float %a) { +; CHECK-LABEL: name: test_intrinsic_trunc +; CHECK: [[A:%[0-9]+]]:_(s32) = COPY $s0 +; CHECK: [[RES:%[0-9]+]]:_(s32) = G_INTRINSIC_TRUNC [[A]] +; CHECK: $s0 = COPY [[RES]] +  %res = call float @llvm.trunc.f32(float %a) +  ret float %res +} + +declare float @llvm.round.f32(float) +define float @test_intrinsic_round(float %a) { +; CHECK-LABEL: name: test_intrinsic_round +; CHECK: [[A:%[0-9]+]]:_(s32) = COPY $s0 +; CHECK: [[RES:%[0-9]+]]:_(s32) = G_INTRINSIC_ROUND [[A]] +; CHECK: $s0 = COPY [[RES]] +  %res = call float @llvm.round.f32(float %a) +  ret float %res +} +  declare i32 @llvm.ctlz.i32(i32, i1)  define i32 @test_ctlz_intrinsic_zero_not_undef(i32 %a) {  ; CHECK-LABEL: name: test_ctlz_intrinsic_zero_not_undef diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir index ccaf16e5153..d5206cc995d 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir @@ -78,6 +78,12 @@  # DEBUG-NEXT: G_BITCAST (opcode {{[0-9]+}}): 2 type indices  # DEBUG:      .. the first uncovered type index: 2, OK  # +# DEBUG-NEXT: G_INTRINSIC_TRUNC (opcode {{[0-9]+}}): 1 type index +# DEBUG:      .. type index coverage check SKIPPED: no rules defined +# +# DEBUG-NEXT: G_INTRINSIC_ROUND (opcode {{[0-9]+}}): 1 type index +# DEBUG:      .. type index coverage check SKIPPED: no rules defined +#  # DEBUG-NEXT: G_LOAD (opcode {{[0-9]+}}): 2 type indices  # DEBUG:      .. type index coverage check SKIPPED: user-defined predicate detected  #  | 

