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| author | Tim Northover <tnorthover@apple.com> | 2014-12-03 17:49:26 +0000 |
|---|---|---|
| committer | Tim Northover <tnorthover@apple.com> | 2014-12-03 17:49:26 +0000 |
| commit | 293d414380579a21fb58fa2894ec297e43f7f6f8 (patch) | |
| tree | 6b327b299af175eb0f8e61d1731742a37a460b44 | |
| parent | 089791db484475ef9bad85f4be900b2e3145fdce (diff) | |
| download | bcm5719-llvm-293d414380579a21fb58fa2894ec297e43f7f6f8.tar.gz bcm5719-llvm-293d414380579a21fb58fa2894ec297e43f7f6f8.zip | |
AArch64: fix wrong-endian parameter passing.
The blocked arguments code didn't take account of the hacks needed to support
it.
llvm-svn: 223247
| -rw-r--r-- | llvm/lib/Target/AArch64/AArch64ISelLowering.cpp | 6 | ||||
| -rw-r--r-- | llvm/test/CodeGen/AArch64/arm64-aapcs-be.ll | 18 |
2 files changed, 21 insertions, 3 deletions
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp index 622b0e1d73d..ee31dbff28e 100644 --- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp +++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp @@ -2107,7 +2107,8 @@ SDValue AArch64TargetLowering::LowerFormalArguments( unsigned ArgSize = VA.getValVT().getSizeInBits() / 8; uint32_t BEAlign = 0; - if (ArgSize < 8 && !Subtarget->isLittleEndian()) + if (!Subtarget->isLittleEndian() && ArgSize < 8 && + !Ins[i].Flags.isInConsecutiveRegs()) BEAlign = 8 - ArgSize; int FI = MFI->CreateFixedObject(ArgSize, ArgOffset + BEAlign, true); @@ -2661,7 +2662,8 @@ AArch64TargetLowering::LowerCall(CallLoweringInfo &CLI, unsigned OpSize = Flags.isByVal() ? Flags.getByValSize() * 8 : VA.getValVT().getSizeInBits(); OpSize = (OpSize + 7) / 8; - if (!Subtarget->isLittleEndian() && !Flags.isByVal()) { + if (!Subtarget->isLittleEndian() && !Flags.isByVal() && + !Flags.isInConsecutiveRegs()) { if (OpSize < 8) BEAlign = 8 - OpSize; } diff --git a/llvm/test/CodeGen/AArch64/arm64-aapcs-be.ll b/llvm/test/CodeGen/AArch64/arm64-aapcs-be.ll index 77e2b0f717b..f27570acc82 100644 --- a/llvm/test/CodeGen/AArch64/arm64-aapcs-be.ll +++ b/llvm/test/CodeGen/AArch64/arm64-aapcs-be.ll @@ -21,4 +21,20 @@ entry: ; CHECK-DAG: strh w{{[0-9]}}, [sp, #14] ; CHECK-DAG: strb w{{[0-9]}}, [sp, #7] ret i32 %call -}
\ No newline at end of file +} + +define float @test_block_addr([8 x float], [1 x float] %in) { +; CHECK-LABEL: test_block_addr: +; CHECK: ldr s0, [sp] + %val = extractvalue [1 x float] %in, 0 + ret float %val +} + +define void @test_block_addr_callee() { +; CHECK-LABEL: test_block_addr_callee: +; CHECK: str {{[a-z0-9]+}}, [sp] +; CHECK: bl test_block_addr + %val = insertvalue [1 x float] undef, float 0.0, 0 + call float @test_block_addr([8 x float] undef, [1 x float] %val) + ret void +} |
