add support for the commuted form of the test instruction, rdar://8018260.

llvm-svn: 113352

2 files changed, 17 insertions, 0 deletions

diff --git a/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp b/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
index 90bd4e3d1b5..7d62c466b27 100644
--- a/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
+++ b/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
@@ -856,6 +856,16 @@ ParseInstruction(StringRef Name, SMLoc NameLoc,
       std::swap(Operands[1], Operands[2]);
     }
 
+  // The assembler accepts "testX <reg>, <mem>" and "testX <mem>, <reg>" as
+  // synonyms.  Our tables only have the "<mem>, <reg>" form, so if we see the
+  // other operand order, swap them.
+  if (Name == "testb" || Name == "testw" || Name == "testl" || Name == "testq")
+    if (Operands.size() == 3 &&
+        static_cast<X86Operand*>(Operands[1])->isReg() &&
+        static_cast<X86Operand*>(Operands[2])->isMem()) {
+      std::swap(Operands[1], Operands[2]);
+    }
+  
   return false;
 }
 
diff --git a/llvm/test/MC/AsmParser/X86/x86_32-new-encoder.s b/llvm/test/MC/AsmParser/X86/x86_32-new-encoder.s
index ed8ee868196..6d9d7ed4074 100644
--- a/llvm/test/MC/AsmParser/X86/x86_32-new-encoder.s
+++ b/llvm/test/MC/AsmParser/X86/x86_32-new-encoder.s
@@ -452,3 +452,10 @@ sysret
 sysretl
 // CHECK: sysretl
 // CHECK: encoding: [0x0f,0x07]
+
+// rdar://8018260
+testl	%ecx, -24(%ebp)
+// CHECK: testl	-24(%ebp), %ecx
+testl	-24(%ebp), %ecx
+// CHECK: testl	-24(%ebp), %ecx
+