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| author | Daniel Sanders <daniel_l_sanders@apple.com> | 2017-09-19 12:56:36 +0000 |
|---|---|---|
| committer | Daniel Sanders <daniel_l_sanders@apple.com> | 2017-09-19 12:56:36 +0000 |
| commit | 28887fe54842fbfbb89b8789280c6a0f3d43ef31 (patch) | |
| tree | f6fb51fad3adffde0e27066a474606d8a70583f5 | |
| parent | ebbde1409f1a4eb5ef0550d72fdd11848f4fbf69 (diff) | |
| download | bcm5719-llvm-28887fe54842fbfbb89b8789280c6a0f3d43ef31.tar.gz bcm5719-llvm-28887fe54842fbfbb89b8789280c6a0f3d43ef31.zip | |
[globalisel] Add support for intrinsic_w_chain.
This maps directly to G_INTRINSIC_W_SIDE_EFFECTS.
llvm-svn: 313627
3 files changed, 33 insertions, 3 deletions
diff --git a/llvm/include/llvm/Target/GlobalISel/SelectionDAGCompat.td b/llvm/include/llvm/Target/GlobalISel/SelectionDAGCompat.td index b7b9e73eaf6..212f2e3b269 100644 --- a/llvm/include/llvm/Target/GlobalISel/SelectionDAGCompat.td +++ b/llvm/include/llvm/Target/GlobalISel/SelectionDAGCompat.td @@ -66,6 +66,7 @@ def : GINodeEquiv<G_FPOW, fpow>; def : GINodeEquiv<G_FEXP2, fexp2>; def : GINodeEquiv<G_FLOG2, flog2>; def : GINodeEquiv<G_INTRINSIC, intrinsic_wo_chain>; +def : GINodeEquiv<G_INTRINSIC_W_SIDE_EFFECTS, intrinsic_w_chain>; def : GINodeEquiv<G_BR, br>; // Specifies the GlobalISel equivalents for SelectionDAG's ComplexPattern. diff --git a/llvm/test/CodeGen/X86/GlobalISel/select-intrinsic-x86-flags-read-u32.mir b/llvm/test/CodeGen/X86/GlobalISel/select-intrinsic-x86-flags-read-u32.mir new file mode 100644 index 00000000000..33ffc6e790c --- /dev/null +++ b/llvm/test/CodeGen/X86/GlobalISel/select-intrinsic-x86-flags-read-u32.mir @@ -0,0 +1,27 @@ +# RUN: llc -mtriple=i386-- -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s + +--- | + define void @read_flags() { ret void } +... + +--- +# Check that we select a the x86.flags.read.u32 intrinsic into a RDFLAGS +# instruction. Also check that we constrain the register class of the COPY to +# gr32. +# CHECK-LABEL: name: read_flags +name: read_flags +legalized: true +regBankSelected: true + +# CHECK: registers: +# CHECK-NEXT: - { id: 0, class: gr32, preferred-register: '' } +registers: + - { id: 0, class: gpr } + +# CHECK: body: +# CHECK: %0 = RDFLAGS32 +body: | + bb.0: + %0(s32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.x86.flags.read.u32) + %rax = COPY %0(s32) +... diff --git a/llvm/utils/TableGen/GlobalISelEmitter.cpp b/llvm/utils/TableGen/GlobalISelEmitter.cpp index 4e7d5dc5174..5a85503e710 100644 --- a/llvm/utils/TableGen/GlobalISelEmitter.cpp +++ b/llvm/utils/TableGen/GlobalISelEmitter.cpp @@ -2038,9 +2038,11 @@ GlobalISelEmitter::createAndImportSelDAGMatcher(InstructionMatcher &InsnMatcher, for (unsigned i = 0, e = Src->getNumChildren(); i != e; ++i) { TreePatternNode *SrcChild = Src->getChild(i); - // For G_INTRINSIC, the operand immediately following the defs is an - // intrinsic ID. - if (SrcGIOrNull->TheDef->getName() == "G_INTRINSIC" && i == 0) { + // For G_INTRINSIC/G_INTRINSIC_W_SIDE_EFFECTS, the operand immediately + // following the defs is an intrinsic ID. + if ((SrcGIOrNull->TheDef->getName() == "G_INTRINSIC" || + SrcGIOrNull->TheDef->getName() == "G_INTRINSIC_W_SIDE_EFFECTS") && + i == 0) { if (const CodeGenIntrinsic *II = Src->getIntrinsicInfo(CGP)) { OperandMatcher &OM = InsnMatcher.addOperand(OpIdx++, SrcChild->getName(), TempOpIdx); |

