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| author | Hal Finkel <hfinkel@anl.gov> | 2015-02-12 22:43:52 +0000 |
|---|---|---|
| committer | Hal Finkel <hfinkel@anl.gov> | 2015-02-12 22:43:52 +0000 |
| commit | 271e9f2870e2374358e4888f674627543f1117a9 (patch) | |
| tree | c7e457d4a366370cf92da642748a702eb0dcc015 | |
| parent | 7d71622c8fd0846d99cd0fb8878ecf255848de0a (diff) | |
| download | bcm5719-llvm-271e9f2870e2374358e4888f674627543f1117a9.tar.gz bcm5719-llvm-271e9f2870e2374358e4888f674627543f1117a9.zip | |
[SDAG] Don't try to use FP_EXTEND/FP_ROUND for int<->fp promotions
The PowerPC backend has long promoted some floating-point vector operations
(such as select) to integer vector operations. Unfortunately, this behavior was
broken by r216555. When using FP_EXTEND/FP_ROUND for promotions, we must check
that both the old and new types are floating-point types. Otherwise, we must
use BITCAST as we did prior to r216555 for everything.
llvm-svn: 228969
| -rw-r--r-- | llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp | 8 | ||||
| -rw-r--r-- | llvm/test/CodeGen/PowerPC/vsel-prom.ll | 23 |
2 files changed, 28 insertions, 3 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp index 11e6b38f076..3a8c276e261 100644 --- a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp @@ -390,7 +390,8 @@ SDValue VectorLegalizer::Promote(SDValue Op) { if (Op.getOperand(j) .getValueType() .getVectorElementType() - .isFloatingPoint()) + .isFloatingPoint() && + NVT.isVector() && NVT.getVectorElementType().isFloatingPoint()) Operands[j] = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Op.getOperand(j)); else Operands[j] = DAG.getNode(ISD::BITCAST, dl, NVT, Op.getOperand(j)); @@ -399,8 +400,9 @@ SDValue VectorLegalizer::Promote(SDValue Op) { } Op = DAG.getNode(Op.getOpcode(), dl, NVT, Operands); - if (VT.isFloatingPoint() || - (VT.isVector() && VT.getVectorElementType().isFloatingPoint())) + if ((VT.isFloatingPoint() && NVT.isFloatingPoint()) || + (VT.isVector() && VT.getVectorElementType().isFloatingPoint() && + NVT.isVector() && NVT.getVectorElementType().isFloatingPoint())) return DAG.getNode(ISD::FP_ROUND, dl, VT, Op, DAG.getIntPtrConstant(0)); else return DAG.getNode(ISD::BITCAST, dl, VT, Op); diff --git a/llvm/test/CodeGen/PowerPC/vsel-prom.ll b/llvm/test/CodeGen/PowerPC/vsel-prom.ll new file mode 100644 index 00000000000..dd219ec0da6 --- /dev/null +++ b/llvm/test/CodeGen/PowerPC/vsel-prom.ll @@ -0,0 +1,23 @@ +; RUN: llc -mcpu=pwr7 < %s | FileCheck %s +target datalayout = "E-m:e-i64:64-n32:64" +target triple = "powerpc64-unknown-linux-gnu" + +; Function Attrs: nounwind +define void @Compute_Lateral() #0 { +entry: + br i1 undef, label %if.then, label %if.end + +if.then: ; preds = %entry + unreachable + +if.end: ; preds = %entry + %0 = select i1 undef, <2 x double> undef, <2 x double> zeroinitializer + %1 = extractelement <2 x double> %0, i32 1 + store double %1, double* undef, align 8 + ret void + +; CHECK-LABEL: @Compute_Lateral +} + +attributes #0 = { nounwind } + |
