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| author | Dan Gohman <gohman@apple.com> | 2008-02-27 21:12:32 +0000 |
|---|---|---|
| committer | Dan Gohman <gohman@apple.com> | 2008-02-27 21:12:32 +0000 |
| commit | 26854f242ecc308439873582396d329959cc756f (patch) | |
| tree | 8ef09522d9872488aa66f34a7e4fa210838d4c36 | |
| parent | 06516b124b333b76868909315dafbe332f9b34d2 (diff) | |
| download | bcm5719-llvm-26854f242ecc308439873582396d329959cc756f.tar.gz bcm5719-llvm-26854f242ecc308439873582396d329959cc756f.zip | |
Don't hard-code the mask size to be 32, which is incorrect on ppc64
and was causing aborts with the new APInt changes. This may also be
fixing an obscure ppc64 bug.
llvm-svn: 47692
| -rw-r--r-- | llvm/lib/Target/PowerPC/PPCISelLowering.cpp | 8 | ||||
| -rw-r--r-- | llvm/test/CodeGen/PowerPC/mask64.ll | 27 |
2 files changed, 32 insertions, 3 deletions
diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp index 3cf39a0093e..5500e37aaec 100644 --- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp +++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp @@ -741,16 +741,18 @@ bool PPCTargetLowering::SelectAddressRegReg(SDOperand N, SDOperand &Base, APInt LHSKnownZero, LHSKnownOne; APInt RHSKnownZero, RHSKnownOne; DAG.ComputeMaskedBits(N.getOperand(0), - APInt::getAllOnesValue(32), + APInt::getAllOnesValue(N.getOperand(0) + .getValueSizeInBits()), LHSKnownZero, LHSKnownOne); if (LHSKnownZero.getBoolValue()) { DAG.ComputeMaskedBits(N.getOperand(1), - APInt::getAllOnesValue(32), + APInt::getAllOnesValue(N.getOperand(1) + .getValueSizeInBits()), RHSKnownZero, RHSKnownOne); // If all of the bits are known zero on the LHS or RHS, the add won't // carry. - if ((LHSKnownZero | RHSKnownZero) == ~0U) { + if (~(LHSKnownZero | RHSKnownZero) == 0) { Base = N.getOperand(0); Index = N.getOperand(1); return true; diff --git a/llvm/test/CodeGen/PowerPC/mask64.ll b/llvm/test/CodeGen/PowerPC/mask64.ll new file mode 100644 index 00000000000..69d2200212f --- /dev/null +++ b/llvm/test/CodeGen/PowerPC/mask64.ll @@ -0,0 +1,27 @@ +; RUN: llvm-as < %s | llc + +target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f128:64:128" +target triple = "powerpc64-apple-darwin9.2.0" + %struct.re_pattern_buffer = type <{ i8*, i64, i8, [7 x i8] }> + +define i32 @xre_search_2(%struct.re_pattern_buffer* %bufp, i32 %range) nounwind { +entry: + br i1 false, label %bb16, label %bb49 + +bb16: ; preds = %entry + %tmp19 = load i8** null, align 1 ; <i8*> [#uses=1] + %tmp21 = load i8* %tmp19, align 1 ; <i8> [#uses=1] + switch i8 %tmp21, label %bb49 [ + i8 0, label %bb45 + i8 1, label %bb34 + ] + +bb34: ; preds = %bb16 + ret i32 0 + +bb45: ; preds = %bb16 + ret i32 -1 + +bb49: ; preds = %bb16, %entry + ret i32 0 +} |
