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| author | Craig Topper <craig.topper@intel.com> | 2018-02-27 06:00:38 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@intel.com> | 2018-02-27 06:00:38 +0000 |
| commit | 264707bae481194d1d45c6adda043733c5a9de32 (patch) | |
| tree | 16ca1bf8e5a919e30c2932bb48179f623e48215a | |
| parent | b424cd5d61cf01ad84b5cf56c9600a004a58d34d (diff) | |
| download | bcm5719-llvm-264707bae481194d1d45c6adda043733c5a9de32.tar.gz bcm5719-llvm-264707bae481194d1d45c6adda043733c5a9de32.zip | |
[X86] Simplify if condition. NFC
SSE2 implies SSE1 and we already covered f32 in the SSE1 check so we don't need to check f32 in the SSE2 check.
llvm-svn: 326170
| -rw-r--r-- | llvm/lib/Target/X86/X86ISelLowering.cpp | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index 0cb4b30f30b..4a9e7e7cb41 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -18434,7 +18434,7 @@ SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const { // are available or VBLENDV if AVX is available. // Otherwise FP cmovs get lowered into a less efficient branch sequence later. if (Cond.getOpcode() == ISD::SETCC && - ((Subtarget.hasSSE2() && (VT == MVT::f32 || VT == MVT::f64)) || + ((Subtarget.hasSSE2() && VT == MVT::f64) || (Subtarget.hasSSE1() && VT == MVT::f32)) && VT == Cond.getOperand(0).getSimpleValueType() && Cond->hasOneUse()) { SDValue CondOp0 = Cond.getOperand(0), CondOp1 = Cond.getOperand(1); |

