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| author | Chris Lattner <sabre@nondot.org> | 2004-02-10 20:25:13 +0000 |
|---|---|---|
| committer | Chris Lattner <sabre@nondot.org> | 2004-02-10 20:25:13 +0000 |
| commit | 259e98ed2713925a8e90ac8ab3f94043bd4f78ba (patch) | |
| tree | c7bc05f59bec25f3bca4f0135b13761177359d3f | |
| parent | 2711c12f48fd51171e8715eab25435b698dd2f37 (diff) | |
| download | bcm5719-llvm-259e98ed2713925a8e90ac8ab3f94043bd4f78ba.tar.gz bcm5719-llvm-259e98ed2713925a8e90ac8ab3f94043bd4f78ba.zip | |
Tighten up checks
llvm-svn: 11274
| -rw-r--r-- | llvm/lib/Target/X86/X86InstrInfo.cpp | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/llvm/lib/Target/X86/X86InstrInfo.cpp b/llvm/lib/Target/X86/X86InstrInfo.cpp index fc72ba31369..8911562bfc8 100644 --- a/llvm/lib/Target/X86/X86InstrInfo.cpp +++ b/llvm/lib/Target/X86/X86InstrInfo.cpp @@ -42,8 +42,8 @@ bool X86InstrInfo::isNOPinstr(const MachineInstr &MI) const { // Make sure the instruction is EXACTLY `xchg ax, ax' if (MI.getOpcode() == X86::XCHGrr16) { const MachineOperand &op0 = MI.getOperand(0), &op1 = MI.getOperand(1); - if (op0.isMachineRegister() && op0.getMachineRegNum() == X86::AX && - op1.isMachineRegister() && op1.getMachineRegNum() == X86::AX) { + if (op0.isPhysicalRegister() && op0.getReg() == X86::AX && + op1.isPhysicalRegister() && op1.getReg() == X86::AX) { return true; } } |
