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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2019-09-16 04:21:10 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2019-09-16 04:21:10 +0000 |
| commit | 255d157672262c5a4d5a4241d99610b02edaa459 (patch) | |
| tree | 056869ee6f463bc8a5c4246dd8b5fe14a941f9c5 | |
| parent | bc8de8a8da704c748cfcb1ad5a348cb234a4fcb8 (diff) | |
| download | bcm5719-llvm-255d157672262c5a4d5a4241d99610b02edaa459.tar.gz bcm5719-llvm-255d157672262c5a4d5a4241d99610b02edaa459.zip | |
AMDGPU/GlobalISel: Remove illegal select tests
These fail in a release build.
llvm-svn: 371955
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-constant.mir | 74 |
1 files changed, 0 insertions, 74 deletions
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-constant.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-constant.mir index 9c09ac4698e..23c01d3339c 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-constant.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-constant.mir @@ -196,43 +196,6 @@ body: | --- -name: load_constant_v3s32 -legalized: true -regBankSelected: true -tracksRegLiveness: true - -body: | - bb.0: - liveins: $sgpr0_sgpr1 - - ; GFX6-LABEL: name: load_constant_v3s32 - ; GFX6: liveins: $sgpr0_sgpr1 - ; GFX6: [[COPY:%[0-9]+]]:sgpr(p4) = COPY $sgpr0_sgpr1 - ; GFX6: [[LOAD:%[0-9]+]]:sreg_96(<3 x s32>) = G_LOAD [[COPY]](p4) :: (load 12, align 4, addrspace 4) - ; GFX6: $sgpr0_sgpr1_sgpr2 = COPY [[LOAD]](<3 x s32>) - ; GFX7-LABEL: name: load_constant_v3s32 - ; GFX7: liveins: $sgpr0_sgpr1 - ; GFX7: [[COPY:%[0-9]+]]:sgpr(p4) = COPY $sgpr0_sgpr1 - ; GFX7: [[LOAD:%[0-9]+]]:sreg_96(<3 x s32>) = G_LOAD [[COPY]](p4) :: (load 12, align 4, addrspace 4) - ; GFX7: $sgpr0_sgpr1_sgpr2 = COPY [[LOAD]](<3 x s32>) - ; GFX8-LABEL: name: load_constant_v3s32 - ; GFX8: liveins: $sgpr0_sgpr1 - ; GFX8: [[COPY:%[0-9]+]]:sgpr(p4) = COPY $sgpr0_sgpr1 - ; GFX8: [[LOAD:%[0-9]+]]:sreg_96(<3 x s32>) = G_LOAD [[COPY]](p4) :: (load 12, align 4, addrspace 4) - ; GFX8: $sgpr0_sgpr1_sgpr2 = COPY [[LOAD]](<3 x s32>) - ; GFX10-LABEL: name: load_constant_v3s32 - ; GFX10: liveins: $sgpr0_sgpr1 - ; GFX10: [[COPY:%[0-9]+]]:sgpr(p4) = COPY $sgpr0_sgpr1 - ; GFX10: [[LOAD:%[0-9]+]]:sreg_96(<3 x s32>) = G_LOAD [[COPY]](p4) :: (load 12, align 4, addrspace 4) - ; GFX10: $sgpr0_sgpr1_sgpr2 = COPY [[LOAD]](<3 x s32>) - %0:sgpr(p4) = COPY $sgpr0_sgpr1 - %1:sgpr(<3 x s32>) = G_LOAD %0 :: (load 12, align 4, addrspace 4) - $sgpr0_sgpr1_sgpr2 = COPY %1 - -... - ---- - name: load_constant_v4s32_align4 legalized: true regBankSelected: true @@ -422,43 +385,6 @@ body: | --- -name: load_constant_s96 -legalized: true -regBankSelected: true -tracksRegLiveness: true - -body: | - bb.0: - liveins: $sgpr0_sgpr1 - - ; GFX6-LABEL: name: load_constant_s96 - ; GFX6: liveins: $sgpr0_sgpr1 - ; GFX6: [[COPY:%[0-9]+]]:sgpr(p4) = COPY $sgpr0_sgpr1 - ; GFX6: [[LOAD:%[0-9]+]]:sgpr(s96) = G_LOAD [[COPY]](p4) :: (load 12, align 4, addrspace 4) - ; GFX6: $sgpr0_sgpr1_sgpr2 = COPY [[LOAD]](s96) - ; GFX7-LABEL: name: load_constant_s96 - ; GFX7: liveins: $sgpr0_sgpr1 - ; GFX7: [[COPY:%[0-9]+]]:sgpr(p4) = COPY $sgpr0_sgpr1 - ; GFX7: [[LOAD:%[0-9]+]]:sreg_96(s96) = G_LOAD [[COPY]](p4) :: (load 12, align 4, addrspace 4) - ; GFX7: $sgpr0_sgpr1_sgpr2 = COPY [[LOAD]](s96) - ; GFX8-LABEL: name: load_constant_s96 - ; GFX8: liveins: $sgpr0_sgpr1 - ; GFX8: [[COPY:%[0-9]+]]:sgpr(p4) = COPY $sgpr0_sgpr1 - ; GFX8: [[LOAD:%[0-9]+]]:sreg_96(s96) = G_LOAD [[COPY]](p4) :: (load 12, align 4, addrspace 4) - ; GFX8: $sgpr0_sgpr1_sgpr2 = COPY [[LOAD]](s96) - ; GFX10-LABEL: name: load_constant_s96 - ; GFX10: liveins: $sgpr0_sgpr1 - ; GFX10: [[COPY:%[0-9]+]]:sgpr(p4) = COPY $sgpr0_sgpr1 - ; GFX10: [[LOAD:%[0-9]+]]:sreg_96(s96) = G_LOAD [[COPY]](p4) :: (load 12, align 4, addrspace 4) - ; GFX10: $sgpr0_sgpr1_sgpr2 = COPY [[LOAD]](s96) - %0:sgpr(p4) = COPY $sgpr0_sgpr1 - %1:sgpr(s96) = G_LOAD %0 :: (load 12, align 4, addrspace 4) - $sgpr0_sgpr1_sgpr2 = COPY %1 - -... - ---- - name: load_constant_s128_align4 legalized: true regBankSelected: true |
