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authorAhmed Bougacha <ahmed.bougacha@gmail.com>2014-12-04 23:52:15 +0000
committerAhmed Bougacha <ahmed.bougacha@gmail.com>2014-12-04 23:52:15 +0000
commit24ebb93da175d023057ec1b10da24eae4cd2701b (patch)
treeac28be2018c1e327df8e6043839a707ac73eb82a
parent3dcdb8d285c9915311c64d7a576048f218a83745 (diff)
downloadbcm5719-llvm-24ebb93da175d023057ec1b10da24eae4cd2701b.tar.gz
bcm5719-llvm-24ebb93da175d023057ec1b10da24eae4cd2701b.zip
[X86] Delete dead code in fcopysign lowering. NFC.
r32900 introduced custom lowering for fcopysign, with two checks to change the magnitude value's type if it's larger/smaller than the sign value's type. r32932 replaced that code for the smaller case. r43205 did the same for the larger case, but left the old code, now dead. llvm-svn: 223415
-rw-r--r--llvm/lib/Target/X86/X86ISelLowering.cpp11
1 files changed, 0 insertions, 11 deletions
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 7976d33397e..9409626124d 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -14477,17 +14477,6 @@ static SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) {
false, false, false, 16);
SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1);
- // Shift sign bit right or left if the two operands have different types.
- if (SrcVT.bitsGT(VT)) {
- // Op0 is MVT::f32, Op1 is MVT::f64.
- SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, SignBit);
- SignBit = DAG.getNode(X86ISD::FSRL, dl, MVT::v2f64, SignBit,
- DAG.getConstant(32, MVT::i32));
- SignBit = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, SignBit);
- SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, SignBit,
- DAG.getIntPtrConstant(0));
- }
-
// Clear first operand sign bit.
CV.clear();
if (VT == MVT::f64) {
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