Thumb assembly parsing and encoding for LDR(immediate) form T2.

llvm-svn: 138050

3 files changed, 25 insertions, 1 deletions

diff --git a/llvm/lib/Target/ARM/ARMInstrThumb.td b/llvm/lib/Target/ARM/ARMInstrThumb.td
index 8d4fa19d9f2..0c7e349698b 100644
--- a/llvm/lib/Target/ARM/ARMInstrThumb.td
+++ b/llvm/lib/Target/ARM/ARMInstrThumb.td
@@ -189,11 +189,13 @@ def t_addrmode_is1 : Operand<i32>,
 
 // t_addrmode_sp := sp + imm8 * 4
 //
+def t_addrmode_sp_asm_operand : AsmOperandClass { let Name = "MemThumbSPI"; }
 def t_addrmode_sp : Operand<i32>,
                     ComplexPattern<i32, 2, "SelectThumbAddrModeSP", []> {
   let EncoderMethod = "getAddrModeThumbSPOpValue";
   let DecoderMethod = "DecodeThumbAddrModeSP";
   let PrintMethod = "printThumbAddrModeSPOperand";
+  let ParserMatchClass = t_addrmode_sp_asm_operand;
   let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
 }
 
diff --git a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
index 58d01e8bd02..b6fce294f2a 100644
--- a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
+++ b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
@@ -626,7 +626,15 @@ public:
     // Immediate offset, multiple of 4 in range [0, 124].
     if (!Mem.OffsetImm) return true;
     int64_t Val = Mem.OffsetImm->getValue();
-    return Val >= 0 && Val < 125 && (Val % 4) == 0;
+    return Val >= 0 && Val <= 124 && (Val % 4) == 0;
+  }
+  bool isMemThumbSPI() const {
+    if (Kind != Memory || Mem.OffsetRegNum != 0 || Mem.BaseRegNum != ARM::SP)
+      return false;
+    // Immediate offset, multiple of 4 in range [0, 1020].
+    if (!Mem.OffsetImm) return true;
+    int64_t Val = Mem.OffsetImm->getValue();
+    return Val >= 0 && Val <= 1020 && (Val % 4) == 0;
   }
   bool isMemImm8Offset() const {
     if (Kind != Memory || Mem.OffsetRegNum != 0)
@@ -992,6 +1000,13 @@ public:
     Inst.addOperand(MCOperand::CreateImm(Val));
   }
 
+  void addMemThumbSPIOperands(MCInst &Inst, unsigned N) const {
+    assert(N == 2 && "Invalid number of operands!");
+    int64_t Val = Mem.OffsetImm ? (Mem.OffsetImm->getValue() / 4) : 0;
+    Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
+    Inst.addOperand(MCOperand::CreateImm(Val));
+  }
+
   void addPostIdxImm8Operands(MCInst &Inst, unsigned N) const {
     assert(N == 1 && "Invalid number of operands!");
     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
diff --git a/llvm/test/MC/ARM/basic-thumb-instructions.s b/llvm/test/MC/ARM/basic-thumb-instructions.s
index a11de561c7c..9d19f33d724 100644
--- a/llvm/test/MC/ARM/basic-thumb-instructions.s
+++ b/llvm/test/MC/ARM/basic-thumb-instructions.s
@@ -182,8 +182,15 @@ _func:
         ldr r1, [r5]
         ldr r2, [r6, #32]
         ldr r3, [r7, #124]
+        ldr r1, [sp]
+        ldr r2, [sp, #24]
+        ldr r3, [sp, #1020]
+
 
 @ CHECK: ldr	r1, [r5]                @ encoding: [0x29,0x68]
 @ CHECK: ldr	r2, [r6, #32]           @ encoding: [0x32,0x6a]
 @ CHECK: ldr	r3, [r7, #124]          @ encoding: [0xfb,0x6f]
+@ CHECK: ldr	r1, [sp]                @ encoding: [0x00,0x99]
+@ CHECK: ldr	r2, [sp, #24]           @ encoding: [0x06,0x9a]
+@ CHECK: ldr	r3, [sp, #1020]         @ encoding: [0xff,0x9b]