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| author | Ahmed Bougacha <ahmed.bougacha@gmail.com> | 2015-05-22 21:37:17 +0000 |
|---|---|---|
| committer | Ahmed Bougacha <ahmed.bougacha@gmail.com> | 2015-05-22 21:37:17 +0000 |
| commit | 236f9040d0f01391c45fd8fa0b0528a21a4ffec8 (patch) | |
| tree | 1f267cb31647064a8060c894df14e1bb4e06af96 | |
| parent | 95ee81daf64c0e36c2869ea3eadc035497935491 (diff) | |
| download | bcm5719-llvm-236f9040d0f01391c45fd8fa0b0528a21a4ffec8.tar.gz bcm5719-llvm-236f9040d0f01391c45fd8fa0b0528a21a4ffec8.zip | |
[AArch64][CGP] Sink zext feeding stxr/stlxr into the same block.
The usual CodeGenPrepare trickery, on a target-specific intrinsic.
Without this, the expansion of atomics will usually have the zext
be hoisted out of the loop, defeating the various patterns we have
to catch this precise case.
Differential Revision: http://reviews.llvm.org/D9930
llvm-svn: 238054
| -rw-r--r-- | llvm/lib/CodeGen/CodeGenPrepare.cpp | 10 | ||||
| -rw-r--r-- | llvm/test/CodeGen/AArch64/arm64-atomic.ll | 6 |
2 files changed, 12 insertions, 4 deletions
diff --git a/llvm/lib/CodeGen/CodeGenPrepare.cpp b/llvm/lib/CodeGen/CodeGenPrepare.cpp index f37a2874b25..cf2b0a29b84 100644 --- a/llvm/lib/CodeGen/CodeGenPrepare.cpp +++ b/llvm/lib/CodeGen/CodeGenPrepare.cpp @@ -1397,6 +1397,16 @@ bool CodeGenPrepare::OptimizeCallInst(CallInst *CI, bool& ModifiedDT) { } return false; } + case Intrinsic::aarch64_stlxr: + case Intrinsic::aarch64_stxr: { + ZExtInst *ExtVal = dyn_cast<ZExtInst>(CI->getArgOperand(0)); + if (!ExtVal || !ExtVal->hasOneUse() || + ExtVal->getParent() == CI->getParent()) + return false; + // Sink a zext feeding stlxr/stxr before it, so it can be folded into it. + ExtVal->moveBefore(CI); + return true; + } } if (TLI) { diff --git a/llvm/test/CodeGen/AArch64/arm64-atomic.ll b/llvm/test/CodeGen/AArch64/arm64-atomic.ll index fa07e9f2e91..9136fb6271b 100644 --- a/llvm/test/CodeGen/AArch64/arm64-atomic.ll +++ b/llvm/test/CodeGen/AArch64/arm64-atomic.ll @@ -2,12 +2,11 @@ define i32 @val_compare_and_swap(i32* %p, i32 %cmp, i32 %new) #0 { ; CHECK-LABEL: val_compare_and_swap: -; CHECK-NEXT: ubfx x[[NEWVAL_REG:[0-9]+]], x2, #0, #32 ; CHECK-NEXT: [[LABEL:.?LBB[0-9]+_[0-9]+]]: ; CHECK-NEXT: ldaxr [[RESULT:w[0-9]+]], [x0] ; CHECK-NEXT: cmp [[RESULT]], w1 ; CHECK-NEXT: b.ne [[LABEL2:.?LBB[0-9]+_[0-9]+]] -; CHECK-NEXT: stxr [[SCRATCH_REG:w[0-9]+]], w[[NEWVAL_REG]], [x0] +; CHECK-NEXT: stxr [[SCRATCH_REG:w[0-9]+]], w2, [x0] ; CHECK-NEXT: cbnz [[SCRATCH_REG]], [[LABEL]] ; CHECK-NEXT: [[LABEL2]]: %pair = cmpxchg i32* %p, i32 %cmp, i32 %new acquire acquire @@ -17,12 +16,11 @@ define i32 @val_compare_and_swap(i32* %p, i32 %cmp, i32 %new) #0 { define i32 @val_compare_and_swap_rel(i32* %p, i32 %cmp, i32 %new) #0 { ; CHECK-LABEL: val_compare_and_swap_rel: -; CHECK-NEXT: ubfx x[[NEWVAL_REG:[0-9]+]], x2, #0, #32 ; CHECK-NEXT: [[LABEL:.?LBB[0-9]+_[0-9]+]]: ; CHECK-NEXT: ldaxr [[RESULT:w[0-9]+]], [x0] ; CHECK-NEXT: cmp [[RESULT]], w1 ; CHECK-NEXT: b.ne [[LABEL2:.?LBB[0-9]+_[0-9]+]] -; CHECK-NEXT: stlxr [[SCRATCH_REG:w[0-9]+]], w[[NEWVAL_REG]], [x0] +; CHECK-NEXT: stlxr [[SCRATCH_REG:w[0-9]+]], w2, [x0] ; CHECK-NEXT: cbnz [[SCRATCH_REG]], [[LABEL]] ; CHECK-NEXT: [[LABEL2]]: %pair = cmpxchg i32* %p, i32 %cmp, i32 %new acq_rel monotonic |
