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| author | Carey Williams <carey.williams@arm.com> | 2018-01-19 16:55:23 +0000 |
|---|---|---|
| committer | Carey Williams <carey.williams@arm.com> | 2018-01-19 16:55:23 +0000 |
| commit | 22c49c6470201d01f830a56d4c742a90d5248106 (patch) | |
| tree | 1b387e60448417f5700bf29ece7483c02d08e80c | |
| parent | 74a1eef7c4f73bcb7d6fe923ca20f301e638edba (diff) | |
| download | bcm5719-llvm-22c49c6470201d01f830a56d4c742a90d5248106.tar.gz bcm5719-llvm-22c49c6470201d01f830a56d4c742a90d5248106.zip | |
Test commit
llvm-svn: 322958
| -rw-r--r-- | llvm/lib/Target/AArch64/AArch64ISelLowering.cpp | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp index d721e7205c9..b41e43ac2c5 100644 --- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp +++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp @@ -8839,7 +8839,7 @@ static SDValue performConcatVectorsCombine(SDNode *N, static SDValue tryCombineFixedPointConvert(SDNode *N, TargetLowering::DAGCombinerInfo &DCI, SelectionDAG &DAG) { - // Wait 'til after everything is legalized to try this. That way we have + // Wait until after everything is legalized to try this. That way we have // legal vector types and such. if (DCI.isBeforeLegalizeOps()) return SDValue(); |
